Updated comment.

libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd

@@ -19,9 +19,11 @@
 --
 -------------------------------------------------------------------------------
 
+-- Author : P.Donker  okt. 2020, added bsn_time_offset
+--
 -- Purpose :
 --   Start a periodic block sync interval and maintain a block sequence
---   number
+--   number according to the PPS and BSN grid defined in [1].
 -- Description:
 --   When dp_on is low then all outputs are low. When dp_on is high, the 
 --   output sync starts pulsing after bsn_time_offset (in clk cycles) with 
@@ -29,19 +31,25 @@
 --   sop and eop will be active.
 --   Alternatively, one can assert dp_on while dp_on_pps is high to 
 --   start the data path on the next PPS.
+--   The src_out.sync always happens at the src_out.sop.
+--   If nof_clk_per_sync / g_block_size is an integer than all src_out.sync
+--   intervals will have nof_clk_per_sync clk cycles, else nof_clk_per_sync
+--   is the average number of clock cycles between src_out.sync and then the
+--   number of blocks per sync intervals will vary between c_nof_block_hi
+--   and c_nof_block_lo.
 --   The dp_on is asynchronous. The dp_bsn_source_v2 takes care that
 --   src_out.valid starts with a src_out.sop and that src_out.valid can
 --   only go low after a src_out.eop, to ensure that src_out only produces
 --   complete sop-eop blocks that enter the subsequent processing.
---   The bs_start is active at the first src_out.sop after dp_on went high.
+--   The bs_restart is active at the first src_out.sop after dp_on went high.
 -- Remarks:
 -- . Starting the data path is only possible from the dp_off state, so one
 --   has to disable (dp_on='0') the data path before restarting it.
 -- . Effectively dp_on_status = src_out.valid, because when the BSN source
 --   is on, then src_out.valid = '1' at every clk cycle.
 --
--- author : P.Donker  okt. 2020, added bsn_time_offset
+-- References:
+-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -70,7 +78,7 @@ ENTITY dp_bsn_source_v2 IS
     nof_clk_per_sync        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
     bsn_init                : IN  STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
     bsn_time_offset         : IN  STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
-    current_bsn_time_offset : OUT STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);  -- output for monitoring purpose in test bench.
+    current_bsn_time_offset : OUT STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
 
     src_out                 : OUT t_dp_sosi  -- only uses sync, bsn[], valid, sop and eop
   );
@@ -81,6 +89,8 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
 
   CONSTANT c_block_size_cnt_w : NATURAL := ceil_log2(g_block_size);
   CONSTANT c_block_cnt_zero   : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
+  CONSTANT c_nof_block_lo     : NATURAL := g_nof_clk_per_sync / g_block_size;
+  CONSTANT c_nof_block_hi     : NATURAL := ceil_div(g_nof_clk_per_sync, g_block_size);
 
   -- The state machine starts synchronously via s_bsn_time_offset, s_dp_on_sop to s_dp_on, or it starts
   -- directly to s_dp_on. When in dp_on it loops between s_dp_on and s_dp_on_eop for every block.
@@ -145,7 +155,6 @@ BEGIN
     nxt_bsn_time_offset_cnt     <= bsn_time_offset_cnt;
     nxt_current_bsn_time_offset <= bsn_time_offset;
 
-
     IF UNSIGNED(clk_cnt) = UNSIGNED(nof_clk_per_sync) - 1 THEN
       nxt_clk_cnt <=  (OTHERS=>'0');
       nxt_sync    <= '1';  -- will set src_out.sync on next src_out.sop
@@ -219,7 +228,6 @@ BEGIN
     END CASE;
   END PROCESS;
 
-
   p_clk : PROCESS(rst, clk)
   BEGIN
     IF rst='1' THEN
@@ -247,5 +255,3 @@ BEGIN
   END PROCESS;
 
 END rtl;
-
-