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RTSD
HDL
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032a28c7
Commit
032a28c7
authored
2 years ago
by
Eric Kooistra
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Clarify blocks_per_sync >= 1 and duration of BG sync interval.
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9bc6aa96
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!297
Resolve L2SDP-837 "B"
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libraries/base/diag/src/vhdl/diag_block_gen.vhd
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032a28c7
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@@ -37,6 +37,13 @@
-- The samples_per_packet >= 2, because the in the p_comb state machine the
-- eop cannot occur at the sop.
--
-- The blocks_per_sync >= 1, so it is possible to have one block per sync
-- interval.
--
-- The BG sync interval takes blocks_per_sync * (samples_per_packet +
-- gapsize) clock cylces. However in case of back pressure from out_siso
-- the BG sync interval become longer, due to clock cycles with valid = '0'.
--
-- The MM reading starts at mem_low_adrs when the BG is first enabled. If
-- the mem_high_adrs-mem_low_adrs+1 < samples_per_packet then the reading
-- wraps and continues from mem_low_adrs. For every new block the reading
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