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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -52,7 +52,7 @@ ENTITY ddrctrl IS
     g_nof_streams     : NATURAL                                             := 12;                                            -- number of input streams
     g_data_w          : NATURAL                                             := 14;                                            -- data with of input data vectors
     g_stop_percentage : NATURAL                                             := 50;
-    g_block_size      : NATURAL                                             := 1024;
+    g_block_size      : NATURAL                                             := 1024
   );
   PORT (
     clk               : IN  STD_LOGIC                                       := '0';
@@ -89,7 +89,7 @@ ARCHITECTURE str OF ddrctrl IS
   CONSTANT  c_wr_fifo_uw_w      : NATURAL                                   := ceil_log2(c_wr_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
   CONSTANT  c_rd_fifo_uw_w      : NATURAL                                   := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
 
-  CONSTANT  c_burstsize         : NATURAL                                   := t_c_tech_ddr.max_burstsize;
+  CONSTANT  c_burstsize         : NATURAL                                   := g_tech_ddr.maxburstsize;
   CONSTANT  c_adr_w             : NATURAL                                   := func_tech_ddr_ctlr_address_w(g_tech_ddr);      -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
   CONSTANT  c_max_adr           : NATURAL                                   := 2**(c_adr_w)-1;                                -- the maximal address that is possible within the vector length of the address
   CONSTANT  c_bim               : NATURAL                                   := (c_max_adr*c_io_ddr_data_w)/(g_block_size*g_nof_streams*g_data_w);   -- the amount of whole blocks that fit in memory.