Fixed the definition of the read register.

libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd

@@ -103,8 +103,9 @@ END diag_data_buffer_dev;
 
 ARCHITECTURE rtl OF diag_data_buffer_dev IS
 
-  CONSTANT c_mm_factor     : NATURAL := ceil_div(g_data_w, c_word_w);  -- must be a power of 2 multiple
+  CONSTANT c_version       : NATURAL := 1; 
 
+  CONSTANT c_mm_factor     : NATURAL := ceil_div(g_data_w, c_word_w);  -- must be a power of 2 multiple
   CONSTANT c_nof_data_mm   : NATURAL := g_nof_data*c_mm_factor;
   CONSTANT g_data_mm_w     : NATURAL := g_data_w/c_mm_factor;
 
@@ -339,7 +340,8 @@ BEGIN
   
   arm_enable     <= reg_wr_arr(2);
   reg_sync_delay <= reg_slv_wr(4*c_word_w-1 DOWNTO 3*c_word_w);
-  reg_slv_rd     <= reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
+  reg_slv_rd     <= TO_UVEC(c_version, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) & 
+                    reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
 
   u_word_cnt : ENTITY common_lib.common_counter
   PORT MAP (