added 16G ddr4 IP and created example design.

...igns/refdesigns/ddr4/ip_arria10_e2sg_ddr4_16g_1600_ed.qar

...esigns/refdesigns/ddr4/unb2c_ed_synth_mb_I_16G.sof.tar.gz

...rd2c/designs/refdesigns/ddr4/unb2c_pins_mbII_ddr4_16g.tcl

...ard2c/designs/refdesigns/ddr4/unb2c_pins_mbI_ddr4_16g.tcl

...s/technology/ip_arria10_e2sg/ddr4_16g_1600/compile_ip.tcl

...chnology/ip_arria10_e2sg/ddr4_16g_1600/copy_hex_files.tcl

...aries/technology/ip_arria10_e2sg/ddr4_16g_1600/hdllib.cfg

...ria10_e2sg/ddr4_16g_1600/ip_arria10_e2sg_ddr4_16g_1600.ip