Corected out_start in case of re-enable, without ctrl_enable going low first.

libraries/base/dp/src/vhdl/dp_bsn_sync_interval.vhd

@@ -43,13 +43,13 @@
 --   output is disable after an in_sosi.eop when ctrl_enable = '0'. If the
 --   output is diabled, then the sosai control fields are forced to '0', the
 --   other sosi fields of the in_sosi are passed on to the out_sosi.
--- * mon_current_bsn:
---   The user can read mon_current_bsn to determine a suitable ctrl_start_bsn
---   in the future.
--- * mon_bsn_at_sync:
---   The user can read mon_current_bsn to determine a suitable ctrl_start_bsn
---   in the future to create a output sync interval that is aligned with the
---   in_sosi.sync.
+-- * mon_input_current_bsn:
+--   The user can read mon_input_current_bsn to determine a suitable
+--   ctrl_start_bsn in the future.
+-- * mon_input_bsn_at_sync:
+--   The user can read mon_input_current_bsn to determine a suitable
+--   ctrl_start_bsn in the future to create a output sync interval that is
+--   aligned with the in_sosi.sync.
 -- * mon_output_enable:
 --   The user can read mon_output_enable to check whether the output is indeed
 --   enabled or not.
@@ -57,12 +57,12 @@
 --   The sync interval calculation is robust to lost in_sosi blocks. As soon
 --   as it receives a new in_sosi block it will try to determine the next
 --   output_sync_bsn, even if blocks were lost for multiple output sync
---   intervals. If mon_output_sync_bsn - mon_current_bsn < 0 then the output
---   sync interval calculation should catch up after some in_sosi blocks. If
---   mon_output_sync_bsn - mon_current_bsn > nof_blk then something went
---   wrong and then it may be necessary to recover using ctrl_enable. If
---   mon_output_sync_bsn - mon_current_bsn < nof_blk and > 0 then that yields
---   the number of blocks until the next output sync.
+--   intervals. If mon_output_sync_bsn - mon_input_current_bsn < 0 then the
+--   output sync interval calculation should catch up after some in_sosi
+--   blocks. If mon_output_sync_bsn - mon_input_current_bsn > nof_blk then
+--   something went wrong and then it may be necessary to recover using
+--   ctrl_enable. If mon_output_sync_bsn - mon_input_current_bsn < nof_blk and
+--   > 0 then that yields the number of blocks until the next output sync.
 -- For example:
 --   . sample period Ts = 5 ns
 --   . g_block_size = 1024 samples
@@ -104,15 +104,16 @@ ENTITY dp_bsn_sync_interval IS
     ctrl_enable_evt       : IN  STD_LOGIC;
     ctrl_interval_size    : IN  NATURAL;  -- = number of data valid per output sync interval
     ctrl_start_bsn        : IN  STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
-    mon_current_bsn      : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-    mon_bsn_at_sync      : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+    mon_input_current_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+    mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
     mon_output_enable     : OUT STD_LOGIC;
     mon_output_sync_bsn   : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
 
     -- Streaming
     in_sosi               : IN t_dp_sosi;
     out_sosi              : OUT t_dp_sosi;
-    out_start            : OUT STD_LOGIC
+    out_start             : OUT STD_LOGIC;
+    out_enable            : OUT STD_LOGIC
   );
 END dp_bsn_sync_interval;
 
@@ -147,8 +148,8 @@ ARCHITECTURE rtl OF dp_bsn_sync_interval IS
 BEGIN
 
   -- Capture monitoring info
-  mon_current_bsn     <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
-  mon_bsn_at_sync     <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
+  mon_input_current_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
+  mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
   mon_output_enable     <= r.output_enable;
   mon_output_sync_bsn   <= r.output_sync_bsn;
 
@@ -224,9 +225,7 @@ BEGIN
       IF in_sosi.sop = '1' THEN
         IF UNSIGNED(in_sosi.bsn) = UNSIGNED(r.start_bsn) THEN
           v.output_enable := '1';
-          IF r.output_enable = '0' THEN
           output_start <= '1';  -- Pulse at start of output enable at start BSN of output sync intervals
-          END IF;
           v.output_sync_bsn := r.start_bsn;
         END IF;
       END IF;
@@ -301,9 +300,11 @@ BEGIN
 
   gen_pipe_out_start : IF g_pipeline = 1 GENERATE
     out_start <= output_start WHEN rising_edge(clk);
+    out_enable <= r.output_enable;
   END GENERATE;
   no_pipe_out_start : IF g_pipeline = 0 GENERATE
     out_start <= output_start;
+    out_enable <= nxt_r.output_enable;
   END GENERATE;
 
 END rtl;