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Commit 00a934eb authored by Eric Kooistra's avatar Eric Kooistra
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Update sim results for c_cable_delay.

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applications/lofar2/libraries/sdp/hdllib.cfg
+ 2
− 2
View file @ 00a934eb
......@@ -46,9 +46,9 @@ regression_test_vhdl =
tb/vhdl/tb_sdp_statistics_offload.vhd
tb/vhdl/tb_tb_sdp_statistics_offload.vhd
tb/vhdl/tb_sdp_crosslets_subband_select.vhd
tb/vhdl/tb_tb_sdp_beamformer_output.vhd
tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
tb/vhdl/tb_tb_sdp_beamformer_output.vhd
[modelsim_project_file]
......
applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+ 48
− 8
View file @ 00a934eb
......@@ -86,12 +86,48 @@
-- 79: 33567 ( 1 32537 ) 32773 -1
--
-- Simulation latency results with this tb
-- Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx
-- _latency: _latency: _latency: _latency:
-- 0: -1 ( 1 0 ) 2053 2075
-- 1: 3862 ( 1 3875 ) 4101 4123
-- 2: 5914 ( 1 5927 ) 6149 6171
-- 3: 7965 ( 1 7978 ) 8197 -1
--
-- # c_cable_delay = 0 * 6.4 ns
-- #
-- # Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx
-- # _latency: _latency: _latency: _latency:
-- # 0: -1 ( 1 0 ) 2053 2075
-- # 1: 3824 ( 1 3837 ) 4101 4123
-- # 2: 5876 ( 1 5889 ) 6149 6171
-- # 3: 7926 ( 1 7939 ) 8197 8219
-- # 4: 9977 ( 1 9990 ) 10245 10267
-- # 5: 12029 ( 1 12042 ) 12293 12315
-- # 6: 14079 ( 1 14092 ) 14341 14363
-- # 7: 16108 ( 1 16121 ) 16389 16411
-- # 8: 18159 ( 1 18172 ) 18437 18459
-- # 9: 20211 ( 1 20224 ) 20485 20507
-- # 10: 22261 ( 1 22274 ) 22533 22555
-- # 11: 24312 ( 1 24325 ) 24581 24603
-- # 12: 26363 ( 1 26376 ) 26629 26651
-- # 13: 28414 ( 1 28427 ) 28677 28699
-- # 14: 30465 ( 1 30478 ) 30725 30747
-- # 15: 32493 ( 1 32506 ) 32773 -1
--
-- # c_cable_delay = 30 * 6.4 ns
-- #
-- # Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx
-- # _latency: _latency: _latency: _latency:
-- # 0: -1 ( 1 0 ) 2053 2075
-- # 1: 3862 ( 1 3875 ) 4101 4123
-- # 2: 5914 ( 1 5927 ) 6149 6171
-- # 3: 7965 ( 1 7978 ) 8197 8219
-- # 4: 10015 ( 1 10028 ) 10245 10267
-- # 5: 12067 ( 1 12080 ) 12293 12315
-- # 6: 14118 ( 1 14131 ) 14341 14363
-- # 7: 16146 ( 1 16159 ) 16389 16411
-- # 8: 18197 ( 1 18210 ) 18437 18459
-- # 9: 20249 ( 1 20262 ) 20485 20507
-- # 10: 22299 ( 1 22312 ) 22533 22555
-- # 11: 24350 ( 1 24363 ) 24581 24603
-- # 12: 26402 ( 1 26415 ) 26629 26651
-- # 13: 28452 ( 1 28465 ) 28677 28699
-- # 14: 30503 ( 1 30516 ) 30725 30747
-- # 15: 32532 ( 1 32545 ) 32773 -1
--
-- - The dp_bsn_align_v2 BSN latency monitor results agree between sim an HW.
-- - The bf_aligned_latency is exactly equal in sim and on HW, because the
......@@ -125,6 +161,7 @@
--
-- Usage:
-- > as 3 or more
-- > add wave -position insertpoint sim:/tb_sdp_beamformer_remote_ring/bf_sum_sosi_arr
-- > run -a
-------------------------------------------------------------------------------
......@@ -143,7 +180,7 @@ use work.tb_sdp_pkg.all;
entity tb_sdp_beamformer_remote_ring is
generic (
g_nof_rn : natural := 2; -- number of nodes in the ring
g_nof_rn : natural := 4; -- number of nodes in the ring
g_nof_sync : natural := 2
);
end tb_sdp_beamformer_remote_ring;
......@@ -160,7 +197,8 @@ architecture tb of tb_sdp_beamformer_remote_ring is
-- c_cable_delay depends a little bit on g_nof_rn, for g_nof_rn = 2 the data goes wrong when
-- c_cable_delay >= 190.
constant c_clk_156_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz
constant c_cable_delay : time := c_clk_156_period * 186;
constant c_nof_delay : natural := 30; --286;
constant c_cable_delay : time := c_clk_156_period * c_nof_delay;
-- BF data
constant c_block_period : natural := c_sdp_N_fft;
......@@ -399,6 +437,8 @@ begin
---------------------------------------------------------------------------
-- Print latency results
---------------------------------------------------------------------------
print_str("c_cable_delay = " & int_to_str(c_nof_delay) & " * 6.4 ns");
print_str("");
print_str("Node: bf_ring_rx bf_rx_align bf_aligned bf_ring_tx");
print_str(" _latency: _latency: _latency: _latency:");
for RN in 0 to c_last_rn loop
......
applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
+ 162
− 43
View file @ 00a934eb
-------------------------------------------------------------------------------
--
-- Copyright 2023
-- Copyright 2024
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
......@@ -60,7 +60,7 @@
-- FPGA_xst_aligned_latency_R(RN) v|
--
-- . XST ring latency results from SDP-ARTS HW:
-- - xst_ring_rx_latency:
-- - xst_ring_rx_latency (SDP-ARTS HW):
-- node 64: -1 -1 -1 -1 -1 -1 -1 -1 1774 1569 1363 1112 906 677 472 266
-- node 65: 249 -1 -1 -1 -1 -1 -1 -1 -1 1776 1579 1352 1113 890 692 472
-- node 66: 466 267 -1 -1 -1 -1 -1 -1 -1 -1 1787 1566 1340 1105 905 685
......@@ -78,7 +78,43 @@
-- node 78: -1 -1 -1 -1 -1 -1 1800 1599 1351 1137 938 693 472 253 -1 -1
-- node 79: -1 -1 -1 -1 -1 -1 -1 1809 1566 1344 1143 899 681 460 259 -1
--
-- - xst_ring_tx_latency:
-- # FPGA_xst_ring_rx_latency_R (sim: c_nof_delay = 12):
-- # 0: -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245
-- # 1: 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442
-- # 2: 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638
-- # 3: 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856
-- # 4: 856 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053
-- # 5: 1053 856 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332
-- # 6: 1332 1053 856 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533
-- # 7: 1533 1332 1053 856 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1 1729
-- # 8: 1729 1533 1332 1053 856 638 442 245 -1 -1 -1 -1 -1 -1 -1 -1
-- # 9: -1 1729 1533 1332 1053 856 638 442 245 -1 -1 -1 -1 -1 -1 -1
-- # 10: -1 -1 1729 1533 1332 1053 856 638 442 245 -1 -1 -1 -1 -1 -1
-- # 11: -1 -1 -1 1729 1533 1332 1053 856 638 442 245 -1 -1 -1 -1 -1
-- # 12: -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245 -1 -1 -1 -1
-- # 13: -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245 -1 -1 -1
-- # 14: -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245 -1 -1
-- # 15: -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245 -1
--
-- # FPGA_xst_ring_rx_latency_R (sim: c_nof_delay = 25):
-- # 0: -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698 481 262
-- # 1: 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698 481
-- # 2: 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698
-- # 3: 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917
-- # 4: 917 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135
-- # 5: 1135 917 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571 1352
-- # 6: 1352 1135 917 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789 1571
-- # 7: 1571 1352 1135 917 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1 1789
-- # 8: 1789 1571 1352 1135 917 698 481 262 -1 -1 -1 -1 -1 -1 -1 -1
-- # 9: -1 1789 1571 1352 1135 917 698 481 262 -1 -1 -1 -1 -1 -1 -1
-- # 10: -1 -1 1789 1571 1352 1135 917 698 481 262 -1 -1 -1 -1 -1 -1
-- # 11: -1 -1 -1 1789 1571 1352 1135 917 698 481 262 -1 -1 -1 -1 -1
-- # 12: -1 -1 -1 -1 1789 1571 1352 1135 917 698 481 262 -1 -1 -1 -1
-- # 13: -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698 481 262 -1 -1 -1
-- # 14: -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698 481 262 -1 -1
-- # 15: -1 -1 -1 -1 -1 -1 -1 1789 1571 1352 1135 917 698 481 262 -1
--
-- - xst_ring_tx_latency (SDP-ARTS HW):
-- node 64: 12 -1 -1 -1 -1 -1 -1 -1 -1 1611 1361 1155 926 698 470 264
-- node 65: 256 12 -1 -1 -1 -1 -1 -1 -1 -1 1583 1363 1143 920 676 476
-- node 66: 470 272 12 -1 -1 -1 -1 -1 -1 -1 -1 1575 1353 1131 892 692
......@@ -96,7 +132,43 @@
-- node 78: -1 -1 -1 -1 -1 -1 -1 1593 1371 1171 928 732 488 268 12 -1
-- node 79: -1 -1 -1 -1 -1 -1 -1 -1 1587 1387 1143 948 702 480 262 12
--
-- - xst_rx_align_latency:
-- # FPGA_xst_ring_tx_latency_R (sim: c_nof_delay = 12):
-- # 0: 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251
-- # 1: 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448
-- # 2: 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645
-- # 3: 645 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862
-- # 4: 862 645 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119
-- # 5: 1119 862 645 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339
-- # 6: 1339 1119 862 645 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539
-- # 7: 1539 1339 1119 862 645 448 251 12 -1 -1 -1 -1 -1 -1 -1 -1
-- # 8: -1 1539 1339 1119 862 645 448 251 12 -1 -1 -1 -1 -1 -1 -1
-- # 9: -1 -1 1539 1339 1119 862 645 448 251 12 -1 -1 -1 -1 -1 -1
-- # 10: -1 -1 -1 1539 1339 1119 862 645 448 251 12 -1 -1 -1 -1 -1
-- # 11: -1 -1 -1 -1 1539 1339 1119 862 645 448 251 12 -1 -1 -1 -1
-- # 12: -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251 12 -1 -1 -1
-- # 13: -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251 12 -1 -1
-- # 14: -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251 12 -1
-- # 15: -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251 12
--
-- # FPGA_xst_ring_tx_latency_R (sim: c_nof_delay = 25):
-- # 0: 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705 488 269
-- # 1: 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705 488
-- # 2: 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705
-- # 3: 705 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924
-- # 4: 924 705 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141
-- # 5: 1141 924 705 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577 1359
-- # 6: 1359 1141 924 705 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1 1577
-- # 7: 1577 1359 1141 924 705 488 269 12 -1 -1 -1 -1 -1 -1 -1 -1
-- # 8: -1 1577 1359 1141 924 705 488 269 12 -1 -1 -1 -1 -1 -1 -1
-- # 9: -1 -1 1577 1359 1141 924 705 488 269 12 -1 -1 -1 -1 -1 -1
-- # 10: -1 -1 -1 1577 1359 1141 924 705 488 269 12 -1 -1 -1 -1 -1
-- # 11: -1 -1 -1 -1 1577 1359 1141 924 705 488 269 12 -1 -1 -1 -1
-- # 12: -1 -1 -1 -1 -1 1577 1359 1141 924 705 488 269 12 -1 -1 -1
-- # 13: -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705 488 269 12 -1 -1
-- # 14: -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705 488 269 12 -1
-- # 15: -1 -1 -1 -1 -1 -1 -1 -1 1577 1359 1141 924 705 488 269 12
--
-- - xst_rx_align_latency (SDP-ARTS HW):
-- node 64: 1 204 434 638 868 1109 1318 1546 1774
-- node 65: 1 214 412 652 852 1109 1315 1532 1756
-- node 66: 1 202 422 622 866 1109 1326 1529 1750
......@@ -114,26 +186,63 @@
-- node 78: 1 206 430 648 868 1109 1332 1559 1772
-- node 79: 1 208 430 650 870 1109 1328 1550 1775
--
-- - xst_aligned_latency:
-- node 64: 2051
-- node 65: 2051
-- node 66: 2051
-- node 67: 2051
-- node 68: 2051
-- node 69: 2051
-- node 70: 2051
-- node 71: 2051
-- node 72: 2051
-- node 73: 2051
-- node 74: 2051
-- node 75: 2051
-- node 76: 2051
-- node 77: 2051
-- node 78: 2051
-- node 79: 2051
-- # FPGA_xst_rx_align_latency_R (sim: c_nof_delay = 12):
-- # 0: 1 199 396 593 810 1109 1308 1506 1702
-- # 1: 1 199 396 593 810 1109 1308 1506 1702
-- # 2: 1 199 396 593 810 1109 1308 1506 1702
-- # 3: 1 199 396 593 810 1109 1308 1506 1702
-- # 4: 1 199 396 593 810 1109 1308 1506 1702
-- # 5: 1 199 396 593 810 1109 1308 1506 1702
-- # 6: 1 199 396 593 810 1109 1308 1506 1702
-- # 7: 1 199 396 593 810 1109 1308 1506 1702
-- # 8: 1 199 396 593 810 1109 1308 1506 1702
-- # 9: 1 199 396 593 810 1109 1308 1506 1702
-- # 10: 1 199 396 593 810 1109 1308 1506 1702
-- # 11: 1 199 396 593 810 1109 1308 1506 1702
-- # 12: 1 199 396 593 810 1109 1308 1506 1702
-- # 13: 1 199 396 593 810 1109 1308 1506 1702
-- # 14: 1 199 396 593 810 1109 1308 1506 1702
-- # 15: 1 199 396 593 810 1109 1308 1506 1702
--
-- # FPGA_xst_rx_align_latency_R (sim: c_nof_delay = 25):
-- # 0: 1 217 436 653 872 1109 1326 1544 1762
-- # 1: 1 217 436 653 872 1109 1326 1544 1762
-- # 2: 1 217 436 653 872 1109 1326 1544 1762
-- # 3: 1 217 436 653 872 1109 1326 1544 1762
-- # 4: 1 217 436 653 872 1109 1326 1544 1762
-- # 5: 1 217 436 653 872 1109 1326 1544 1762
-- # 6: 1 217 436 653 872 1109 1326 1544 1762
-- # 7: 1 217 436 653 872 1109 1326 1544 1762
-- # 8: 1 217 436 653 872 1109 1326 1544 1762
-- # 9: 1 217 436 653 872 1109 1326 1544 1762
-- # 10: 1 217 436 653 872 1109 1326 1544 1762
-- # 11: 1 217 436 653 872 1109 1326 1544 1762
-- # 12: 1 217 436 653 872 1109 1326 1544 1762
-- # 13: 1 217 436 653 872 1109 1326 1544 1762
-- # 14: 1 217 436 653 872 1109 1326 1544 1762
-- # 15: 1 217 436 653 872 1109 1326 1544 1762
--
-- - xst_aligned_latency (SDP-ARTS HW): # FPGA_xst_aligned_latency_R (sim: c_nof_delay = 12, 25):
-- node 64: 2051 # 0: 2051
-- node 65: 2051 # 1: 2051
-- node 66: 2051 # 2: 2051
-- node 67: 2051 # 3: 2051
-- node 68: 2051 # 4: 2051
-- node 69: 2051 # 5: 2051
-- node 70: 2051 # 6: 2051
-- node 71: 2051 # 7: 2051
-- node 72: 2051 # 8: 2051
-- node 73: 2051 # 9: 2051
-- node 74: 2051 # 10: 2051
-- node 75: 2051 # 11: 2051
-- node 76: 2051 # 12: 2051
-- node 77: 2051 # 13: 2051
-- node 78: 2051 # 14: 2051
-- node 79: 2051 # 15: 2051
--
-- Usage:
-- > as 3 or more
-- > add wave -position insertpoint sim:/tb_sdp_crosslets_remote_ring/x_sosi_2arr
-- > run -a
-------------------------------------------------------------------------------
......@@ -163,10 +272,12 @@ architecture tb of tb_sdp_crosslets_remote_ring is
constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
-- Apply cable delay in tech_pll_clk_156_period units, to remain aligned with tr_10GbE sim model
-- . Choose c_cable_delay = 30 * 6.4 ~= 192 ns ~= 38 dp_clk of 5 ns, to match delay seen on HW
-- . Maximum c_cable_delay <= ??? * 6.4 =
-- . Choose c_cable_delay = 16 * 6.4 ~= 102 ns ~= 20 dp_clk of 5 ns, to match delay seen on HW
-- . Minimum c_cable_delay >= 12 * 6.4 = 77 ns ~= 15 dp_clk of 5 ns, else missed blocks in x_sosi
-- . Maximum c_cable_delay <= 29 * 6.4 = 185 ns ~= 37 dp_clk of 5 ns, else missed blocks in x_sosi
constant c_clk_156_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz
constant c_cable_delay : time := c_clk_156_period * 188;
constant c_nof_delay : natural := 20;
constant c_cable_delay : time := c_clk_156_period * c_nof_delay;
-- XST data
constant c_P_sq : natural := g_nof_rn / 2 + 1; -- nof square correlator cells
......@@ -192,9 +303,9 @@ architecture tb of tb_sdp_crosslets_remote_ring is
-- = crosslet subband select block size divided by 2 as it is repacked from 32b to 64b. = 42 longwords
constant c_lane_payload_nof_longwords_xst : natural := c_sdp_N_crosslets_max * c_sdp_S_pn / 2;
constant c_lane_packet_nof_longwords_max : natural := c_lane_payload_nof_longwords_xst + c_ring_dp_hdr_field_size;
-- = 549 + 3 = 552
-- = 54 + 3 = 57
constant c_fifo_tx_fill_margin : natural := 10; -- >= c_fifo_fill_margin = 6 that is used in dp_fifo_fill_eop
constant c_fifo_tx_size_ring : natural := true_log_pow2(c_lane_packet_nof_longwords_max + c_fifo_tx_fill_margin);
constant c_fifo_tx_size_ring : natural := true_log_pow2(c_lane_packet_nof_longwords_max * 2 + c_fifo_tx_fill_margin);
-- = 552 + 6 --> 1024
constant c_fifo_tx_fill_ring : natural := c_fifo_tx_size_ring - c_fifo_tx_fill_margin;
-- = maximum fill level, so rely on eop
......@@ -322,8 +433,8 @@ begin
local_crosslets_sosi_arr(RN) <= stimuli_sosi;
local_crosslets_sosi_arr(RN).data <= TO_DP_SDATA(0);
-- different crosslets value (and /= 0) per node
local_crosslets_sosi_arr(RN).re <= TO_DP_DSP_DATA(RN + c_local_crosslet_re);
local_crosslets_sosi_arr(RN).im <= TO_DP_DSP_DATA(RN + c_local_crosslet_im);
local_crosslets_sosi_arr(RN).re <= TO_DP_DSP_DATA(RN * c_nof_complex + c_local_crosslet_re); -- odd
local_crosslets_sosi_arr(RN).im <= TO_DP_DSP_DATA(RN * c_nof_complex + c_local_crosslet_im); -- even
local_crosslets_sosi_arr(RN).channel <= TO_DP_CHANNEL(0);
local_crosslets_sosi_arr(RN).err <= TO_DP_ERROR(0);
end loop;
......@@ -338,10 +449,10 @@ begin
variable v_offset : natural;
-- print_str()
constant c_nof_col : natural := 1 + g_nof_rn;
constant c_col_w : natural := 5;
constant c_extra_w : natural := 10;
constant c_line_w : natural := c_extra_w + c_nof_col * c_col_w;
constant c_col_w : natural := 6;
constant c_line_w : natural := c_nof_col * c_col_w;
variable v_line : string(1 to c_line_w);
variable v_col : natural;
begin
proc_common_wait_until_low(dp_clk, mm_rst);
proc_common_wait_some_cycles(mm_clk, 10);
......@@ -427,44 +538,52 @@ begin
---------------------------------------------------------------------------
-- Print latency results
---------------------------------------------------------------------------
print_str("c_cable_delay = " & int_to_str(c_nof_delay) & " * 6.4 ns");
print_str("");
print_str("FPGA_xst_ring_rx_latency_R:");
for RN in 0 to c_last_rn loop
-- latency values
v_line := (others => ' ');
-- ring node index
v_line(1 to c_col_w - 2) := int_to_str(RN, c_col_w - 2);
v_line(c_col_w - 1) := ':';
-- latency values
for U in 0 to c_last_rn loop
v_line(c_line_w - c_col_w * (U + 1) + 1 to c_line_w - c_col_w * U) :=
v_col := 1 + U;
v_line(1 + v_col * c_col_w to (v_col + 1) * c_col_w) :=
int_to_str(FPGA_xst_ring_rx_latency_R(RN)(U), c_col_w);
end loop;
-- ring node index
v_line(c_line_w - c_col_w * (c_last_rn + 1) + 1 to c_line_w - c_col_w * c_last_rn) := int_to_str(RN, c_col_w);
print_str(v_line);
end Loop;
print_str("");
print_str("FPGA_xst_ring_tx_latency_R:");
for RN in 0 to c_last_rn loop
-- latency values
v_line := (others => ' ');
-- ring node index
v_line(1 to c_col_w - 2) := int_to_str(RN, c_col_w - 2);
v_line(c_col_w - 1) := ':';
-- latency values
for U in 0 to c_last_rn loop
v_line(c_line_w - c_col_w * (U + 1) + 1 to c_line_w - c_col_w * U) :=
v_col := 1 + U;
v_line(1 + v_col * c_col_w to (v_col + 1) * c_col_w) :=
int_to_str(FPGA_xst_ring_tx_latency_R(RN)(U), c_col_w);
end loop;
-- ring node index
v_line(c_line_w - c_col_w * (c_last_rn + 1) + 1 to c_line_w - c_col_w * c_last_rn) := int_to_str(RN, c_col_w);
print_str(v_line);
end Loop;
print_str("");
print_str("FPGA_xst_rx_align_latency_R:");
for RN in 0 to c_last_rn loop
-- latency values
v_line := (others => ' ');
-- ring node index
v_line(1 to c_col_w - 2) := int_to_str(RN, c_col_w - 2);
v_line(c_col_w - 1) := ':';
-- latency values
for U in 0 to c_P_sq - 1 loop
v_line(c_line_w - c_col_w * (U + 1) + 1 to c_line_w - c_col_w * U) :=
v_col := 1 + U;
v_line(1 + v_col * c_col_w to (v_col + 1) * c_col_w) :=
int_to_str(FPGA_xst_rx_align_latency_R(RN)(U), c_col_w);
end loop;
-- ring node index
v_line(c_line_w - c_col_w * (c_P_sq + 1) + 1 to c_line_w - c_col_w * c_P_sq) := int_to_str(RN, c_col_w);
print_str(v_line);
end Loop;
print_str("");
......
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