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tech_ddr_component_pkg.vhd 65.97 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE tech_ddr_component_pkg IS
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail oct_rdn : IN STD_LOGIC; -- oct.rdn
oct_rup : IN STD_LOGIC; -- .rup
seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC; -- .mem_cke
mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC; -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
oct_rdn : IN STD_LOGIC; -- oct.rdn
oct_rup : IN STD_LOGIC; -- .rup
seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk_in.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk_in.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset_in.reset_n
mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC; -- .mem_cke
mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC; -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(28 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
oct_rdn : IN STD_LOGIC; -- oct.rdn
oct_rup : IN STD_LOGIC; -- .rup
seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
------------------------------------------------------------------------------
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Dual rank version of ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_8g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
------------------------------------------------------------------------------ -- ip_arria10_e1sg
------------------------------------------------------------------------------
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Dual rank version of ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_8g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-- Dual rank version for e2sg
COMPONENT ip_arria10_e2sg_ddr4_8g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
COMPONENT ip_arria10_e2sg_ddr4_8g_2400 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
amm_read_0 : in std_logic := '0'; -- .read
amm_write_0 : in std_logic := '0'; -- .write
amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
amm_readdatavalid_0 : out std_logic; -- .readdatavalid
emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_a : out std_logic_vector(16 downto 0); -- .mem_a
mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
mem_par : out std_logic_vector(0 downto 0); -- .mem_par
mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
END tech_ddr_component_pkg;
PACKAGE BODY tech_ddr_component_pkg IS
END tech_ddr_component_pkg;