ddr_testdriver.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>                  
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tech_ddr_component_pkg.all;

-- This module instantiates the Altera MegaWizard DDR3 controller and
-- test driver for both modules.
-- It adds a control state machine so the Nios can offload the task of
-- monitoring the test progress.

-- Nov 13th 2014
-- name changed to ddr_testdriver
-- added generic for technology independance
-- added support for DDR4 in Arria10
-- parameterise bus widths

ENTITY ddr_testdriver IS
  generic (
	g_SELECT_MODULE			: IN INTEGER := 5		-- 0 for original guess using 'normal' high peed controller,
													-- 1 for Micron MT4JSF12864HZ-1G4D1 at 800MT/s using high speed controller II
													-- 2 for Micron MT4JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II
													-- 3 for Micron MT8JSF12864HZ-1G4D1 at 800MT/s using high speed controller II
													-- 4 for Micron MT8JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II
													-- 5 for Micron MT16JSF51264HZ-1G4D1 at 1066MT/s using high speed controller II
													-- 6 for Micron MT8JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II with bitwise pnf
	);
  PORT (
    -- GENERAL
    CLK                    : IN    STD_LOGIC; -- System Clock
    reset_n                : IN    STD_LOGIC; -- active low reset

    -- SO-DIMM Memory Bank I
    MB_I_EVENT             : IN    STD_LOGIC;
    MB_I_DQ                : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    MB_I_A                 : OUT   STD_LOGIC_VECTOR(15 DOWNTO 0);
    MB_I_BA                : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0);
    MB_I_DQS               : INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
    MB_I_DQS_N             : INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
    MB_I_DM                : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
    MB_I_CAS               : OUT   STD_LOGIC;
    MB_I_RAS               : OUT   STD_LOGIC;
    MB_I_WE                : OUT   STD_LOGIC;
    MB_I_RESET             : OUT   STD_LOGIC;
    MB_I_ODT               : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
    MB_I_CK                : INOUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
    MB_I_CK_N              : INOUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
    MB_I_CKE               : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);