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tb_ddrctrl_repack.vhd

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    tb_ddrctrl_repack.vhd 7.29 KiB
    -------------------------------------------------------------------------------
    --
    -- Copyright 2022
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- Licensed under the Apache License, Version 2.0 (the "License");
    -- you may not use this file except in compliance with the License.
    -- You may obtain a copy of the License at
    --
    --     http://www.apache.org/licenses/LICENSE-2.0
    --
    -- Unless required by applicable law or agreed to in writing, software
    -- distributed under the License is distributed on an "AS IS" BASIS,
    -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    -- See the License for the specific language governing permissions and
    -- limitations under the License.
    --
    -------------------------------------------------------------------------------
    -- Author: Job van Wee
    -- Purpose: Self checking and self-stopping tb for ddrctrl_repack.vhd
    -- Usage:
    -- > run -a
    
    LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE IEEE.MATH_REAL.ALL;
    USE technology_lib.technology_pkg.ALL;
    USE tech_ddr_lib.tech_ddr_pkg.ALL;
    USE dp_lib.dp_stream_pkg.ALL;
    USE common_lib.common_mem_pkg.ALL;
    USE common_lib.common_pkg.ALL;
    
    ENTITY tb_ddrctrl_repack IS
      GENERIC (
    
        g_tech_ddr                : t_c_tech_ddr                                           := c_tech_ddr4_8g_1600m;                    -- type of memory
        g_in_data_w               : NATURAL                                                := 168;                                     -- input data vector with
        g_sim_lengt               : NATURAL                                                := 52                                       -- amount of times there wil be input data for ddrctrl_repack in this testbench
    
      );
    END tb_ddrctrl_repack;
    
    ARCHITECTURE tb OF tb_ddrctrl_repack IS
    
      -- constants for running testbench
      CONSTANT  c_clk_freq        : NATURAL                                                := 200;                                     -- clock freqency in MHz
      CONSTANT  c_clk_period      : TIME                                                   := (10**6 / c_clk_freq) * 1 ps;             -- clock period, 5 ns
    
      -- constant for readability
      CONSTANT  c_out_data_w      : NATURAL                                                := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
    
      -- function for making total data vector
      FUNCTION  c_total_vector_init RETURN STD_LOGIC_VECTOR IS
        VARIABLE temp             : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0);
      BEGIN
        FOR I IN 0 TO g_sim_lengt-1 LOOP
          temp(g_in_data_w*(I+1)-1 DOWNTO g_in_data_w*I) := TO_UVEC(I, g_in_data_w);
        END LOOP;
        RETURN temp;
      END FUNCTION c_total_vector_init;
    
      -- constant for running the test
      CONSTANT  c_total_vector    : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0)   := c_total_vector_init;                     -- vector which contains all input data vectors to make it easy to fill ctr_vector
    
    
      -- input signals for ddrctrl_repack.vhd
      SIGNAL    clk               : STD_LOGIC                                              := '1';                                     -- clock signal
      SIGNAL    rst               : STD_LOGIC                                              := '0';                                     -- reset signal
      SIGNAL    in_data           : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0)               := (OTHERS => '0');                         -- input data signal for ddrctrl_repack
    
      -- output signals from ddrctrl_repack.vhd
      SIGNAL    out_of            : NATURAL                                                := 0;                                       -- output signal from ddrctrl_repack to determen how high the overflow is
      SIGNAL    out_sosi          : t_dp_sosi                                              := c_dp_sosi_init;                          -- output data signal form ddrctrl_repack
    
      -- testbench signal
      SIGNAL    tb_end            : STD_LOGIC                                              := '0';                                     -- signal to turn the testbench off
    
      -- singals for running the test
      SIGNAL    in_data_cnt       : NATURAL                                                := 0;                                       -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
      SIGNAL    test_running      : STD_LOGIC                                              := '0';                                     -- signal to tell wheter the testing has started
    
    BEGIN
    
      -- Generating clock
      clk                 <= NOT clk OR tb_end AFTER c_clk_period/2;
    
      -- Excecuting the test
      p_test : PROCESS
      BEGIN
    
        -- start the test
        tb_end            <= '0';
        WAIT UNTIL rising_edge(clk);                                                                                                   -- align to rising edge
        WAIT FOR c_clk_period*5;
        rst <= '1';
        WAIT FOR c_clk_period*1;
        rst <= '0';
        WAIT FOR c_clk_period*1;
        test_running      <= '1';                                                                                                      -- start of test
    
        -- filling the input vector g_sim_lengt amount of times
        make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
          in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
          WAIT FOR c_clk_period*1;
          in_data_cnt     <= in_data_cnt + 1;
        END LOOP;
        test_running      <= '0';
    
        -- stopping the testbench
        WAIT FOR c_clk_period*5;
        tb_end            <= '1';
        ASSERT FALSE                                                                                                                      REPORT "Test: OK"                                                                                                           SEVERITY FAILURE;
      END PROCESS;
    
      -- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
      p_verify : PROCESS
    
      VARIABLE  ctr_of            : NATURAL                                                := 0;
      VARIABLE  out_data_cnt      : NATURAL                                                := 0;
    
      BEGIN
      WAIT UNTIL rising_edge(clk);
      IF test_running = '1' AND out_sosi.valid = '1' THEN
        out_data_cnt      := out_data_cnt+1;
        IF out_data_cnt mod 2 = 0 THEN
          ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
          ASSERT ctr_of                               = out_of                                                                              REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
        END IF;
        ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1))    REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt)                                               SEVERITY ERROR;
      END IF;
      END PROCESS;
    
    
      -- DUT
      u_ddrctrl_repack : ENTITY work.ddrctrl_repack
      GENERIC MAP (
        g_tech_ddr        => g_tech_ddr,
        g_in_data_w       => g_in_data_w
      )
      PORT MAP (
        clk               => clk,
        rst               => rst,
        in_data           => in_data,
    
        out_of            => out_of,
        out_sosi          => out_sosi
      );
    
    END tb;