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Eric Kooistra authoredEric Kooistra authored
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hdllib.cfg 372 B
hdl_lib_name = fpga_sense
hdl_library_clause_name = fpga_sense_lib
hdl_lib_uses_synth = common technology tech_fpga_temp_sens tech_fpga_voltage_sens
hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
src/vhdl/fpga_sense.vhd
test_bench_files =
regression_test_vhdl =
# no self checking tb available yet
[modelsim_project_file]
[quartus_project_file]