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hdllib.cfg

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    hdllib.cfg 856 B 
    hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram
hdl_lib_uses_sim = 
hdl_lib_technology = 
hdl_lib_disclose_library_clause_names =
    ip_stratixiv_ram      ip_stratixiv_ram_lib
    ip_arria10_ram        ip_arria10_ram_lib
    ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
    ip_arria10_e1sg_ram   ip_arria10_e1sg_ram_lib
    ip_arria10_e2sg_ram   ip_arria10_e2sg_ram_lib

synth_files =
    tech_memory_component_pkg.vhd
    tech_memory_ram_cr_cw.vhd
    tech_memory_ram_crw_crw.vhd
    tech_memory_ram_crwk_crw.vhd
    tech_memory_ram_r_w.vhd
    tech_memory_rom_r.vhd

test_bench_files =

regression_test_vhdl = 
    # no self checking tb available yet


[modelsim_project_file]


[quartus_project_file]