tech_ddr.vhd

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--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
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-- Purpose: Technology independent component for DDR memory access.
-- Description:
--   The component also supports different types of DDR, so DDR3 and DDR4.
-- Remark:

LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE work.tech_ddr_pkg.ALL;

ENTITY tech_ddr IS
  GENERIC (
    g_sim_model            : BOOLEAN := FALSE;  -- TRUE: use fast behavioural model, requires no external memory (uses memory array).
    g_technology           : NATURAL := c_tech_select_default;
    g_tech_ddr             : t_c_tech_ddr
  );
  PORT (
    -- PLL reference clock
    ref_clk           : IN    STD_LOGIC;
    ref_rst           : IN    STD_LOGIC;

    -- Controller user interface
    ctlr_gen_clk      : OUT   STD_LOGIC;
    ctlr_gen_rst      : OUT   STD_LOGIC;
    ctlr_gen_clk_2x   : OUT   STD_LOGIC;
    ctlr_gen_rst_2x   : OUT   STD_LOGIC;

    ctlr_mosi         : IN    t_mem_ctlr_mosi;
    ctlr_miso         : OUT   t_mem_ctlr_miso;

    term_ctrl_out     : OUT   t_tech_ddr3_phy_terminationcontrol;
    term_ctrl_in      : IN    t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;

    -- DDR3 PHY interface
    phy3_in            : IN    t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
    phy3_io            : INOUT t_tech_ddr3_phy_io;
    phy3_ou            : OUT   t_tech_ddr3_phy_ou;
    
    -- DDR4 PHY interface
    phy4_in            : IN    t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
    phy4_io            : INOUT t_tech_ddr4_phy_io;
    phy4_ou            : OUT   t_tech_ddr4_phy_ou
  );
END tech_ddr;


ARCHITECTURE str OF tech_ddr IS

BEGIN

  -----------------------------------------------------------------------------
  -- Technology IP cores
  ----------------------------------------------------------------------------- 
  gen_ip: IF g_sim_model = FALSE GENERATE
    gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
      u0 : ENTITY work.tech_ddr_stratixiv
      GENERIC MAP (g_tech_ddr)
      PORT MAP (ref_clk, ref_rst,
                ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
                ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in,
                phy3_in, phy3_io, phy3_ou);
    END GENERATE;
    
    gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
      u0 : ENTITY work.tech_ddr_arria10
      GENERIC MAP (g_tech_ddr)
      PORT MAP (ref_clk, ref_rst,
                ctlr_gen_clk, ctlr_gen_rst,
                ctlr_mosi, ctlr_miso,
                phy4_in, phy4_io, phy4_ou);
    END GENERATE;
  END GENERATE;
 
  -----------------------------------------------------------------------------
  -- Functional simulation model of both the DDR controller and the DDR memory
  -----------------------------------------------------------------------------
  gen_sim_ddr : IF g_sim_model=TRUE GENERATE
    u_sim_ddr : ENTITY work.sim_ddr
    GENERIC MAP (
      g_tech_ddr        => g_tech_ddr
    )
    PORT MAP (
      -- PLL reference clock
      ref_clk           => ref_clk,
      ref_rst           => ref_rst,
    
      -- Controller user interface
      ctlr_gen_clk      => ctlr_gen_clk,
      ctlr_gen_rst      => ctlr_gen_rst,
      ctlr_gen_clk_2x   => ctlr_gen_clk_2x,
      ctlr_gen_rst_2x   => ctlr_gen_rst_2x,
    
      ctlr_mosi         => ctlr_mosi,
      ctlr_miso         => ctlr_miso
    );
  END GENERATE;
  
END str;