tech_eth_10g.vhd

--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------


-- Purpose: Combine mac_10g and 10gbase_r
-- Description:
-- . For c_tech_stratixiv: not available (yet)
--
-- . For c_tech_arria10:
--                __________________
--                |                |
--     tx_snk --->|tech_           |---> tx_serial
--     rx_src <---|eth_10g_arria10 |<--- rx_serial
--                |________________|
--                    |
--                    |
--                  mac_mm
--

LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;

ENTITY tech_eth_10g IS
  GENERIC (
    g_technology          : NATURAL := c_tech_select_default;
    g_sim                 : BOOLEAN := FALSE;
    g_nof_channels        : NATURAL := 1;
    g_pre_header_padding  : BOOLEAN := FALSE
  );
  PORT (
    -- Transceiver PLL reference clock
    tr_ref_clk_644   : IN  STD_LOGIC := '0';   -- 644.531250 MHz for 10GBASE-R
    
    -- MM
    mm_clk           : IN  STD_LOGIC;
    mm_rst           : IN  STD_LOGIC;
    
    mac_mosi         : IN  t_mem_mosi;     -- MAG_10G (CSR), aggregated for all g_nof_channels
    mac_miso         : OUT t_mem_miso; 
    
    -- Clocks
    clk_312          : IN  STD_LOGIC := '0';
    clk_156          : IN  STD_LOGIC := '0';
    rst_156          : IN  STD_LOGIC := '0';
    
    -- ST
    tx_snk_in_arr    : IN  t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ clk_156
    tx_snk_out_arr   : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); 
    
    rx_src_out_arr   : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ clk_156
    rx_src_in_arr    : IN  t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
    
    -- Serial
    tx_serial_arr    : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
    rx_serial_arr    : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0')
  );
END tech_eth_10g;


ARCHITECTURE str OF tech_eth_10g IS

  -- MAG_10G control status registers
  SIGNAL mac_mosi_arr       : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
  SIGNAL mac_miso_arr       : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 

BEGIN
                   
  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
  END GENERATE;
  
  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
    u0 : ENTITY work.tech_eth_10g_arria10
    GENERIC MAP (
      g_sim                 => g_sim,
      g_nof_channels        => g_nof_channels,
      g_pre_header_padding  => g_pre_header_padding
    )
    PORT MAP (
      -- Transceiver PLL reference clock
      tr_ref_clk_644   => tr_ref_clk_644,
      
      -- MM
      mm_clk           => mm_clk,
      mm_rst           => mm_rst,
      
      mac_mosi_arr     => mac_mosi_arr,
      mac_miso_arr     => mac_miso_arr,
      
      -- Clocks
      clk_312          => clk_312,
      clk_156          => clk_156,
      rst_156          => rst_156,
      
      -- ST
      tx_snk_in_arr    => tx_snk_in_arr,       -- 64 bit data @ clk_156
      tx_snk_out_arr   => tx_snk_out_arr, 
      
      rx_src_out_arr   => rx_src_out_arr,      -- 64 bit data @ clk_156
      rx_src_in_arr    => rx_src_in_arr,
      
      -- Serial
      tx_serial_arr    => tx_serial_arr,
      rx_serial_arr    => rx_serial_arr
    );
  END GENERATE;
  
  -----------------------------------------------------------------------------
  -- MM bus mux
  -----------------------------------------------------------------------------
  u_common_mem_mux : ENTITY common_lib.common_mem_mux
  GENERIC MAP (    
    g_nof_mosi    => g_nof_channels,
    g_mult_addr_w => func_tech_mac_10g_csr_addr_w(g_technology) 
  )
  PORT MAP (
    mosi     => mac_mosi,
    miso     => mac_miso,
    mosi_arr => mac_mosi_arr,
    miso_arr => mac_miso_arr
  );  

END str;