common.peripheral.yaml

schema_name: args
schema_version: 1.0
schema_type: peripheral

hdl_library_name: common
hdl_library_description: "Common peripherals for common logic and memory."

peripherals:
  - peripheral_name: common_variable_delay    # pi_common_variable_delay.py ???
    peripheral_description: |
      "The common_variable_delay.vhd logic can delay an input pulse by a number of clock cycles.
       The delay depends on an internal signal input, such that it the delay is not fixed, but
       can be different for different instances.
       The delay is not programmable, but delayed output pulse can be enabled when enable = 1
       or disabled when enable = 0."
    mm_ports:
      # MM port for mms_common_variable_delay.vhd / mms_common_reg.vhd
      - mm_port_name: REG_COMMON_VARIABLE_DELAY
        mm_port_type: REG
        mm_port_description: ""
        fields:
          - - field_name: enable
              field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
              address_offset: 0x0
              mm_width: 1
              access_mode: RW