.gitlab-ci.yml

###############################################################################
#
# Copyright 2022
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
###############################################################################

# Author:
# . Daniel van der Schuur
# Purpose:
# . Define automated test stages for the HDL repository this file belongs to.
# Description:
# . See https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Gitlab+pipeline+automation+to+test+SDPFW+with+OPC+UA

stages:
    - simulation
    - synthesis
    - hardware


###############################################################################
# HDL simulation stage
###############################################################################
sim-compile:
    tags: 
        - fpga
    stage: simulation
    script:
        - echo "Compiling for simulation"
        - mkdir build
        - touch build/info.txt
    artifacts:
        paths:
            - build/

sim-run:
    tags: 
        - fpga
    stage: simulation
    script:
        - echo "Running simulations"
#        - test -f "build/info.txt" # This fails despite having artifact (see 
                                    # sim-compile code block where a folder and
                                    # file are generated and preserved by using
                                    # 'artifacts').

###############################################################################
# HDL synthesis stage
###############################################################################
synth-compile:
    tags: 
        - fpga
    stage: synthesis
    script:
        - echo "Compiling for synthesis"

synth-check-fmax: