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ddrctrl_controller.vhd

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    ddrctrl_controller.vhd 22.29 KiB
    -------------------------------------------------------------------------------
    --
    -- Copyright 2022
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- Licensed under the Apache License, Version 2.0 (the "License");
    -- you may not use this file except in compliance with the License.
    -- You may obtain a copy of the License at
    --
    --     http://www.apache.org/licenses/LICENSE-2.0
    --
    -- Unless required by applicable law or agreed to in writing, software
    -- distributed under the License is distributed on an "AS IS" BASIS,
    -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    -- See the License for the specific language governing permissions and
    -- limitations under the License.
    --
    -------------------------------------------------------------------------------
    -- Author: Job van Wee
    -- Purpose: controller for ddrctrl, decides when to write when to read or when to stop writing or reading.
    --
    -- Description:
    --
    -- Remark:
    --  Use VHDL coding template from:
    --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
    --  
    
    LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib;
    USE IEEE.std_logic_1164.ALL;
    USE IEEE.numeric_std.ALL;
    USE dp_lib.dp_stream_pkg.ALL;
    USE common_lib.common_mem_pkg.ALL;
    USE common_lib.common_pkg.ALL;
    USE tech_ddr_lib.tech_ddr_pkg.ALL;
    
    
    ENTITY ddrctrl_controller IS
      GENERIC (
        g_tech_ddr                : t_c_tech_ddr;
        g_stop_percentage         : NATURAL     := 50;
        g_nof_streams             : NATURAL;    -- 12
        g_out_data_w              : NATURAL;    -- 14
        g_wr_data_w               : NATURAL;    -- 168
        g_rd_fifo_depth           : NATURAL;    -- 256
        g_rd_data_w               : NATURAL;    -- 256
        g_block_size              : NATURAL;    -- 1024
        g_wr_fifo_uw_w            : NATURAL;    -- 8
        g_rd_fifo_uw_w            : NATURAL;    -- 8
        g_max_adr                 : NATURAL;    -- 16128
        g_burstsize               : NATURAL;    -- 64
        g_last_burstsize          : NATURAL;    -- 18
        g_adr_per_b               : NATURAL;    -- 299
        g_bim                     : NATURAL     -- 54
      );
      PORT (
        clk                       : IN  STD_LOGIC;
        rst                       : IN  STD_LOGIC;
    
        -- ddrctrl_input
        inp_of                    : IN  NATURAL;
        inp_sosi                  : IN  t_dp_sosi;
        inp_adr                   : IN  NATURAL;
        inp_bsn_adr               : IN  NATURAL;
        inp_data_stopped          : IN  STD_LOGIC;
        rst_ddrctrl_input_ac      : OUT STD_LOGIC;
    
        -- io_ddr
        dvr_mosi                  : OUT t_mem_ctlr_mosi;