sim_transceiver_deserializer.vhd

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--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------

-- Purpose:
--   Basic deserializer model for fast transceiver simulation
-- Description:
--   See sim_transceiver_serializer.vhd 
-- Remarks:


LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE common_lib.common_pkg.ALL;

ENTITY sim_transceiver_deserializer IS 
  GENERIC(
    g_data_w         : NATURAL := 32;
    g_tr_clk_period  : TIME := 6.4 ns
  );      
  PORT(
    tb_end        : IN  STD_LOGIC := '0';
    
    tr_clk        : IN  STD_LOGIC;
    tr_rst        : IN  STD_LOGIC;

    rx_out_data   : OUT STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
    rx_out_ctrl   : OUT STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);

    rx_serial_in  : IN  STD_LOGIC
  );

END sim_transceiver_deserializer;


ARCHITECTURE beh OF sim_transceiver_deserializer IS

  CONSTANT c_line_clk_period   : TIME    := g_tr_clk_period * 8 / 10 / g_data_w;
  CONSTANT c_tr_clk_period_sim : TIME    := c_line_clk_period * g_data_w * 10 / 8;

  CONSTANT c_nof_bytes_per_data : NATURAL := g_data_w/c_byte_w;

BEGIN

  p_deserialize: PROCESS
    VARIABLE v_rx_out_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
    VARIABLE v_rx_out_ctrl : STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
  BEGIN
    --rx_out_data <= (OTHERS=>'0');
    rx_out_ctrl <= (OTHERS=>'0');
    WAIT UNTIL tr_rst='0' ;

    -- Align to tr_clk
    WAIT UNTIL rising_edge(tr_clk);
    
    WHILE tb_end='0' LOOP
      -- Wait for half of a serial clk period so data is stable when sampling
      WAIT FOR c_line_clk_period/2;
      
      -- Data word deserialization cycle
      FOR byte IN 0 TO c_nof_bytes_per_data-1 LOOP
        -- Deserialize each data byte using 10 bits per byte from the line
        FOR bit IN 0 TO c_byte_w-1 LOOP
          v_rx_out_data(byte*c_byte_w+bit) := rx_serial_in;  -- Get the 8 data bits of the data byte from the line
          WAIT FOR c_line_clk_period;
        END LOOP;
        v_rx_out_ctrl(byte) := rx_serial_in;                 -- Get the 1 control bit from the line for each byte
        WAIT FOR c_line_clk_period;
        --Ignore tenth bit                                   -- Get the 1 unused tenth bit = '0' from the line
        IF byte<c_nof_bytes_per_data-1 THEN
          WAIT FOR c_line_clk_period;  -- exit loop in last half line clock cycle
        END IF;
      END LOOP;
      
      -- Realign to tr_clk rising edge
      WAIT UNTIL rising_edge(tr_clk);

      -- End of this deserialization cycle: the rx data word has been assembled.
      rx_out_data <= v_rx_out_data;
      rx_out_ctrl <= v_rx_out_ctrl;
    END LOOP;

  END PROCESS;

END beh;