tech_pll_component_pkg.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

-- Purpose: IP components declarations for various devices that get wrapped by the tech components

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE tech_pll_component_pkg IS

  -----------------------------------------------------------------------------
  -- ip_stratixiv
  -----------------------------------------------------------------------------
  
  COMPONENT ip_stratixiv_pll_clk200 IS
  GENERIC (
    g_operation_mode   : STRING := "NORMAL";   -- or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
    g_clk0_phase_shift : STRING := "0";
    g_clk1_phase_shift : STRING := "0"
  );
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		c1		: OUT STD_LOGIC ;
		c2		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
  END COMPONENT;
  
  COMPONENT ip_stratixiv_pll_clk200_p6 IS
  GENERIC (
    g_pll_type         : STRING := "Left_Right"; -- "AUTO", "Left_Right", or "Top_Bottom". Set "Left_Right" to direct using PLL_L3 close to CLK pin on UniBoard, because with "AUTO" still a top/bottom PLL may get inferred.
    g_operation_mode   : STRING := "NORMAL";     -- or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
    g_clk0_phase_shift : STRING := "0";          -- = 0 degrees for clk 200 MHz
    g_clk1_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk2_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk3_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk4_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk5_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk6_used        : STRING := "PORT_USED";  -- or "PORT_UNUSED"
    g_clk1_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk2_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk3_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk4_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk5_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk6_divide_by   : NATURAL := 32;          -- = clk 200/32 MHz 
    g_clk1_phase_shift : STRING := "0";          -- = 0     
    g_clk2_phase_shift : STRING := "156";        -- = 011.25
    g_clk3_phase_shift : STRING := "313";        -- = 022.5 
    g_clk4_phase_shift : STRING := "469";        -- = 033.75