tb_common_variable_delay.vhd

-- --------------------------------------------------------------------------
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- --------------------------------------------------------------------------

-- --------------------------------------------------------------------------
-- Author:
-- . Pieter Donker
-- Purpose:
-- . test bench for common_variable_delay.vhd
-- Description:
-- . see common_variable_delay
-- --------------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.common_pkg.ALL;
USE work.common_str_pkg.ALL;
USE work.tb_common_pkg.ALL;

ENTITY tb_common_variable_delay IS
END tb_common_variable_delay;

ARCHITECTURE tb OF tb_common_variable_delay IS

  CONSTANT c_clk_period       : TIME    := 10 ns;
  CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
  CONSTANT c_trigger_latency  : NATURAL := 1;  -- in clk's
  CONSTANT c_delay_arr        : t_natural_arr(0 TO 3) := (0, 1, 3, 12);
  
  SIGNAL tb_end : STD_LOGIC := '0';
  SIGNAL rst    : STD_LOGIC;
  SIGNAL clk    : STD_LOGIC := '0';
  
  SIGNAL delay       : NATURAL   := 0;
  SIGNAL enable      : STD_LOGIC := '0';
  SIGNAL trigger     : STD_LOGIC := '0';
  SIGNAL trigger_dly : STD_LOGIC := '0';
  SIGNAL clk_cnt     : NATURAL   := 0;
BEGIN

  clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
  rst <= '1', '0' AFTER c_clk_period*4;

  -- generate trigger signal
  proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);

  
  p_in_stimuli : PROCESS
  BEGIN
    delay  <= 0;
    enable <= '0';
    
    WAIT UNTIL rst = '0';
    WAIT UNTIL rising_edge(clk);
    
    -- If enable = 0, no trigger_dly is expected, see wave-window
    proc_common_wait_some_cycles(clk, 50);

    
    enable <= '1';
    -- enable trigger output and count clk's between trigger lo-hi and trigger_dly lo-hi
    -- check if counted clk's = c_trigger_latency + delay 
    FOR i IN c_delay_arr'RANGE LOOP
      delay <= c_delay_arr(i);
      clk_cnt <= 0;
      proc_common_wait_until_lo_hi(clk, trigger);
      WHILE trigger_dly = '0' LOOP
        clk_cnt <= clk_cnt + 1;
        proc_common_wait_some_cycles(clk, 1);
      END LOOP;
      ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR; 
      proc_common_wait_some_cycles(clk, 10);
    END LOOP;
    
    enable <= '0';
    proc_common_wait_some_cycles(clk, 10);


    tb_end <= '1';    
    WAIT;
  END PROCESS;

  -- device under test
  u_dut : ENTITY work.common_variable_delay
  PORT MAP (
    rst     => rst,
    clk     => clk,

    delay   => delay,
    enable  => enable,
    in_val  => trigger,
    out_val => trigger_dly
  );
      
END tb;