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tech_fpga_temp_sens.vhd

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    tech_fpga_temp_sens.vhd 2.73 KiB
    -------------------------------------------------------------------------------
    --
    -- Copyright (C) 2015
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- This program is free software: you can redistribute it and/or modify
    -- it under the terms of the GNU General Public License as published by
    -- the Free Software Foundation, either version 3 of the License, or
    -- (at your option) any later version.
    --
    -- This program is distributed in the hope that it will be useful,
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    -- GNU General Public License for more details.
    --
    -- You should have received a copy of the GNU General Public License
    -- along with this program.  If not, see <http://www.gnu.org/licenses/>.
    --
    -------------------------------------------------------------------------------
    
    LIBRARY ieee, technology_lib;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;
    --USE ip_arria10_temp_sense_altera_temp_sense_150.ip_arria10_temp_sense_pkg.all;
    USE work.tech_fpga_temp_sens_component_pkg.ALL;
    USE technology_lib.technology_pkg.ALL;
    USE technology_lib.technology_select_pkg.ALL;
    
    LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
    LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
    LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
    
    
    ENTITY tech_fpga_temp_sens IS
      GENERIC (
        g_technology : NATURAL := c_tech_select_default
      );
    	PORT (
    		corectl : IN  STD_LOGIC             := '0'; -- corectl.corectl
    		eoc     : OUT STD_LOGIC;                    --     eoc.eoc
    		reset   : IN  STD_LOGIC             := '0'; --   reset.reset
    		tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)  -- tempout.tempout
    	);
    END tech_fpga_temp_sens;
    
    ARCHITECTURE str OF tech_fpga_temp_sens IS
    
    BEGIN
    
      gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
    	  u0 : ip_arria10_temp_sense
    		PORT MAP (
    			corectl => corectl, -- corectl.corectl
    			reset   => reset,   --   reset.reset
    			tempout => tempout, -- tempout.tempout
    			eoc     => eoc      --     eoc.eoc
    		);
      END GENERATE;
    
      gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
    	  u0 : ip_arria10_e3sge3_temp_sense
    		PORT MAP (
    			corectl => corectl, -- corectl.corectl
    			reset   => reset,   --   reset.reset
    			tempout => tempout, -- tempout.tempout
    			eoc     => eoc      --     eoc.eoc
    		);
      END GENERATE;
    
      gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
    	  u0 : ip_arria10_e1sg_temp_sense
    		PORT MAP (
    			corectl => corectl, -- corectl.corectl
    			reset   => reset,   --   reset.reset
    			tempout => tempout, -- tempout.tempout
    			eoc     => eoc      --     eoc.eoc
    		);
      END GENERATE;
    
    END ARCHITECTURE;