tech_transceiver_rx_order.vhd

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--
-- Copyright (C) 2013
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
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LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL; 
USE common_lib.common_pkg.ALL;

ENTITY tech_transceiver_rx_order IS
  GENERIC (
    g_data_w  : NATURAL := 16
  );
  PORT (
    rx_clk       : IN  STD_LOGIC;    
    rx_rst       : IN  STD_LOGIC;

    rx_data_in   : IN  STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
    rx_ctrl_in   : IN  STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);   
               
    rx_data_out  : OUT STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
    rx_valid_out : OUT STD_LOGIC
  );
END ENTITY;

ARCHITECTURE rtl OF tech_transceiver_rx_order IS

  SIGNAL in_hi_dat   : STD_LOGIC_VECTOR(g_data_w/2-1 DOWNTO 0);
  SIGNAL in_lo_dat   : STD_LOGIC_VECTOR(g_data_w/2-1 DOWNTO 0);
  SIGNAL in_hi_val   : STD_LOGIC;
  SIGNAL in_lo_val   : STD_LOGIC;

  SIGNAL nxt_rx_data_out : STD_LOGIC_VECTOR(rx_data_out'RANGE);
  SIGNAL nxt_rx_valid_out : STD_LOGIC;
  SIGNAL odd_dat     : STD_LOGIC_VECTOR(in_lo_dat'RANGE);
  SIGNAL nxt_odd_dat : STD_LOGIC_VECTOR(odd_dat'RANGE);
  SIGNAL odd_val     : STD_LOGIC;
  SIGNAL nxt_odd_val : STD_LOGIC;

BEGIN

  in_hi_dat <= rx_data_in(g_data_w-1 DOWNTO g_data_w/2);
  in_hi_val <= NOT rx_ctrl_in(rx_ctrl_in'HIGH);

  in_lo_dat <= rx_data_in(g_data_w/2-1 DOWNTO 0);
  in_lo_val <= NOT rx_ctrl_in(rx_ctrl_in'LOW);

  regs: PROCESS (rx_rst, rx_clk)
  BEGIN
    IF rx_rst='1' THEN
      rx_valid_out <= '0';
      rx_data_out <= (OTHERS => '0');
      odd_val <= '0';
      odd_dat <= (OTHERS => '0');
    ELSIF rising_edge(rx_clk) THEN
      rx_valid_out <= nxt_rx_valid_out;
      rx_data_out <= nxt_rx_data_out;
      odd_val <= nxt_odd_val;
      odd_dat <= nxt_odd_dat;
    END IF;
  END PROCESS;

  odd_proc : PROCESS (in_hi_dat, in_hi_val, in_lo_dat, in_lo_val, odd_dat, odd_val)
  BEGIN
    nxt_odd_val <= '0';

    IF in_hi_val = '1' AND in_lo_val = '0' AND odd_val = '0' THEN
      nxt_odd_val <= '1';
    ELSIF in_hi_val = '1' AND in_lo_val = '1' AND odd_val = '1' THEN
      nxt_odd_val <= '1';
    END IF;

    nxt_odd_dat <= in_hi_dat;
  END PROCESS;


  out_proc : PROCESS (in_hi_dat, in_hi_val, in_lo_dat, in_lo_val, odd_dat, odd_val)
  BEGIN
    nxt_rx_valid_out <= (in_hi_val AND in_lo_val) OR (odd_val AND (in_hi_val OR in_lo_val));
    nxt_rx_data_out <= (OTHERS => '0');

    IF odd_val='0' THEN
      nxt_rx_data_out(2*g_data_w/2-1 DOWNTO 0) <= in_hi_dat & in_lo_dat;
    ELSE
      nxt_rx_data_out(2*g_data_w/2-1 DOWNTO 0) <= in_lo_dat & odd_dat;
    END IF;
  END PROCESS;

END rtl;