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Commit a419db90 authored by Eric Kooistra's avatar Eric Kooistra
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Changed the mmap format, focus is now on using the QSYS slave port names.

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with 68 additions and 121 deletions
gen_rom_mmap.py
+ 68
− 121
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......@@ -33,172 +33,119 @@ import os
import logging
from argparse import ArgumentParser
from args_logger import MyLogger
from py_args_lib import FPGA, RAM, FIFO, Register, PeripheralLibrary, FPGALibrary, ceil_pow2, WIDTH_IN_BYTES
from py_args_lib import FPGA, RAM, FIFO, Register, PeripheralLibrary, FPGALibrary, WORD_SIZE
import pprint
def make_mask(width, offset=0):
_hi_bit = offset + width - 1
_lo_bit = offset
if width == 1:
_mask_str = 'b[{}]'.format(_lo_bit) # use [i] instead of [i:i]
else:
_mask_str = 'b[{}:{}]'.format(_hi_bit, _lo_bit)
#_mask_str = 'b[{}:{}]'.format(_hi_bit, _lo_bit)
return _mask_str
def gen_fpga_map(fpga, fpga_name):
_map_str = []
slave_ports = {}
# pprint.pprint(fpga.address_map)
print("Including slave ports for {}:".format(fpga_name))
map_format_str = ' {:24s} {:4s} {:5s} {:24s} 0x{:08x} {:6d} {:>5s} {:>10s}'
for slave_port_name, slave_port_info in fpga.address_map.items():
# All elements in array have same info, so only need info from first element
if slave_port_info['periph_num'] > 0:
continue
peripheral = slave_port_info['peripheral']
#print("slave_port_info = {}".format(slave_port_info))
slave = slave_port_info['slave']
base = int(slave_port_info['base'])
base_word = int(base / WIDTH_IN_BYTES)
slavename = slave.name()
user_def_name = slave.user_defined_name().upper()
number_of_slaves = str(slave.number_of_slaves())
base = int(slave_port_info['base'])
base_word = int(base / WORD_SIZE)
if isinstance(slave, RAM):
print(' RAM {:23s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
if 'data' in slavename:
slavename = slavename.replace('data', '').strip('_')
_map_str.append(' {:12s} {:12s} {:16s} {:7s} 0x{:08x} {:6d} {:>5s} {:>10s} {:>5s} {:20s}'.format(
peripheral.name(),
slavename,
'data',
print(' RAM {:40s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
_map_str.append(map_format_str.format(
user_def_name,
number_of_slaves,
'RAM',
'data', # EK: TODO should come from yaml field_name
base_word,
slave.number_of_fields(),
slave.access_mode(),
'-',
str(slave.number_of_slaves()),
user_def_name
'-' # EK: TODO should use make_mask() to report field_width of RAM data
))
elif isinstance(slave, FIFO):
print(' FIFO {:23s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
if 'data' in slavename:
slavename = slavename.replace('data', '').strip('_')
_map_str.append(' {:12s} {:12s} {:16s} {:7s} 0x{:08x} {:6d} {:>5s} {:>10s} {:>5s} {:20s}'.format(
peripheral.name(),
slavename,
'data',
print(' FIFO {:40s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
_map_str.append(map_format_str.format(
user_def_name,
number_of_slaves,
'FIFO',
'data', # EK: TODO should come from yaml field_name
base_word,
slave.number_of_fields(),
slave.access_mode(),
'-',
str(slave.number_of_slaves()),
user_def_name
'-' # EK: TODO should use make_mask() to report field_width of FIFO data, there seems no slave.fields
))
elif isinstance(slave, Register):
print(' REG {:23s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
slave_type = "REG" # EK: TODO get slave_type from slave ?
print(' REG {:40s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name))
done = []
number_of_slaves = str(slave.number_of_slaves())
for r in slave.rams:
r_base = base_word + int(r.address_offset() / WIDTH_IN_BYTES)
for f in slave.fields:
field_name = f.name()
#print(f.radix().lower()) # EK: TODO do not use radix in mmap ?
field_name = r.name().strip('0123456789')
# EK: TODO the check on f.number_of_fields() and on done should not be necessary, because the array of fields should only have one element in slave.fields. The slave.number_of_fields() should not have been expanded in slave.
if f.number_of_fields() > 1:
field_name = f.name().strip('0123456789') # strip field array index
if field_name in done:
continue
if field_name in slavename:
slavename = slavename.replace(field_name, '').strip('_')
if field_name not in done:
done.append(field_name)
_map_str.append(' {:12s} {:12s} {:16s} {:7s} 0x{:08x} {:6d} {:>5s} {:>10s} {:>5s} {:20s}'.format(
peripheral.name(),
slavename,
field_name,
'REG',
r_base,
r.number_of_fields(),
r.access_mode(),
make_mask(r.width()),
number_of_slaves,
user_def_name
))
number_of_slaves = '-'
done = []
number_of_slaves = str(slave.number_of_slaves())
for f in slave.fields:
f_base = base_word + int(f.address_offset() / WIDTH_IN_BYTES)
name = "{}_{}_{}".format(peripheral.name(), slave.name(), f.name())
field_group = f.group_name()
if field_group == None:
field_group = '-'
field_name = f.name().strip('0123456789')
if field_name in done:
continue
f_base = base_word + int(f.address_offset() / WORD_SIZE)
if field_name in slavename:
slavename = slavename.replace(field_name, '').strip('_')
if name not in done:
done.append(name)
done.append(field_name)
_map_str.append(' {:12s} {:12s} {:16s} {:7s} 0x{:08x} {:6d} {:>5s} {:>10s} {:>5s} {:20s}'.format(
peripheral.name(),
slavename,
_map_str.append(map_format_str.format(
user_def_name,
number_of_slaves,
slave_type,
field_name,
'REG',
f_base,
f.number_of_fields(),
f.access_mode(),
make_mask(f.width()),
number_of_slaves,
user_def_name
make_mask(f.width(), f.bit_offset())
))
# only log table entry for first field of slave
user_def_name = '-'
number_of_slaves = '-'
"""
# col 1: peripheral-name
# col 2: slave-name
# col 3: field-name
# col 4: field type (REG, RAM, FIFO)
# col 5: field start-address (in words)
# col 6: field address-span (in words)
# col 7: field access-mode (RO, WO, RW)
# col 8: field mask if type is REG else -
# col 9: number of slaves, if - it is part of previous slave.
# col 9: qsys-name
#
# col1 col2 col3 col4 col5 col6 col7 col8 col9
#
system info info REG 0x00000000 32 RO b[31:0] PIO_SYSTEM_INFO
rom_system info info REG 0x00004000 8192 RO b[31:0] ROM_SYSTEM_INFO
ctrl pio_wdi nios_reset REG 0x000000E0 4 WO b[31:0] PIO_WDI
wdi wdi reset_word REG 0x00000C00 1 WO b[31:0] REG_WDI
eth1g tse status REG 0x00000400 1024 RO b[31:0] AVS_ETH_0_TSE
eth1g eth status REG 0x00000020 12 RO b[31:0] AVS_ETH_0_REG
eth1g eth data RAM 0x00000800 1024 RW - AVS_ETH_0_RAM
ppsh ppsh status REG 0x000000EC 1 RO b[31:0] PIO_PPS
ppsh ppsh control REG 0x000000ED 1 RW b[31:0] PIO_PPS
epcs epcs addr REG 0x000000D0 1 WO b[23:0] REG_EPCS
epcs epcs rden REG 0x000000D1 1 WO b[0:0] REG_EPCS
epcs epcs read_bit REG 0x000000D2 1 WO b[0:0] REG_EPCS
epcs epcs write_bit REG 0x000000D3 1 WO b[0:0] REG_EPCS
epcs epcs sector_erase REG 0x000000D4 1 WO b[0:0] REG_EPCS
epcs epcs busy REG 0x000000D5 1 WO b[0:0] REG_EPCS
"""
slave_type = '-'
_map_info = []
_map_info.append('# fpga mm map for {}'.format(fpga_name))
_map_info.append('# col 1: peripheral-name')
_map_info.append('# col 2: slave-name')
_map_info.append('# col 3: field-name')
_map_info.append('# col 4: field type (REG, RAM, FIFO)')
_map_info.append('# col 5: field start-address (in words)')
_map_info.append('# col 6: field address-span (in words)')
_map_info.append('# col 7: field access-mode (RO, WO, RW)')
_map_info.append('# col 8: field mask if type is REG else -')
_map_info.append('# col 9: number of slaves, if - it is part of previous slave.')
_map_info.append('# col 10: qsys-name')
_map_info.append('# col 1: slave port name = user defined QSYS name, if - then it is part of previous slave.')
_map_info.append('# col 2: number of slaves, if - then it is part of previous slave.')
_map_info.append('# col 3: slave_type (REG, RAM, FIFO), if - then it is part of previous slave.')
_map_info.append('# col 4: field_name')
_map_info.append('# col 5: field start address (in words)')
_map_info.append('# col 6: field address span = number of fields (in words)')
_map_info.append('# col 7: field access_mode (RO, WO, RW)')
_map_info.append('# col 8: field bit mask')
_map_info.append('#')
_map_info.append('# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10')
_map_info.append('# ----------- ----------- --------------- ----- ---------- ----- ---- --------- ---- ----------------')
_map_info.append('# col1 col2 col3 col4 col5 col6 col7 col8')
_map_info.append('# ------------------------ ---- ----- ------------------------ ---------- ------ ----- ----------')
out_dir = os.path.join(os.getenv('ARGS_BUILD_DIR'), fpga.board_name.replace('uniboard','unb'), 'args', fpga_name, 'c')
try:
......
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