BugID: 781

Combine write() and write_force() transition into one transition.
The new write() transition allows transition from IDLE and from CHECK to WRITE.
The previous more restricted transition (only from IDLE) was causing some
writes not to happen, most notably writing of WG registers.

MAC/APL/RTCCommon/include/APL/RTCCommon/RegisterState.h

@@ -100,14 +100,13 @@ namespace LOFAR {
 
 	void read         (int i = -1) { tran(IDLE,          READ,          i); }
 	void check        (int i = -1) { tran(IDLE,          CHECK,         i); }
-	void write_force  (int i = -1) { tran(IDLE,          WRITE,         i); }
 	void unmodified   (int i = -1) { tran(CHECK,         IDLE,          i); }
-	void write        (int i = -1) { tran(CHECK,         WRITE,         i); }
 	void read_schedule(int i = -1) { tran(WRITE,         READ,          i); }
 	void read_ack     (int i = -1) { tran(READ,          DONE,          i); }
 	void write_ack    (int i = -1) { tran(WRITE,         DONE,          i); }
 	void read_error   (int i = -1) { tran(READ,          READ_ERROR,    i); }
 	void write_error  (int i = -1) { tran(WRITE,         WRITE_ERROR,   i); }
+	void write        (int i = -1);
 
 	void clear(int i = -1);
 	void reset(int i = -1);

MAC/APL/RTCCommon/src/RegisterState.cc

@@ -95,6 +95,8 @@ void RegisterState::tran(State source, State target, int i)
       m_state(j) = target;
     } else if (target != m_state(j)) {
       LOG_ERROR_STR("tran(" << source << ", " << target << ") failed, current state = " << m_state(j));
+      // for some reason the LOG_ERROR doesn't work in this file so cerr is sometimes used like below
+      //cerr << "tran(" << source << ", " << target << ") failed, current state = " << m_state(j) << endl;
     }
   }
 }
@@ -127,6 +129,34 @@ void RegisterState::clear(int i)
   }
 }
 
+// transition from IDLE or CHECK -> WRITE
+void RegisterState::write(int i)
+{
+  int lb = 0, ub = 0;
+  if (i < 0) {
+    lb = 0;
+    ub = m_state.extent(blitz::firstDim);
+  } else {
+    ASSERT(i >= 0 && i < m_state.extent(blitz::firstDim));
+    lb = i;
+    ub = i + 1;
+  }
+   
+  for (int j = lb; j < ub; j++) {
+    if (IDLE == m_state(j)) {
+      m_state(j) = WRITE;
+    } else if (CHECK == m_state(j)) {
+      m_state(j) = WRITE;
+    } else if (WRITE == m_state(j)) {
+      // already in write state
+    } else {
+      LOG_ERROR_STR("tran to " << WRITE << " from " << m_state(j) << " failed");
+      // for some reason the LOG_ERROR doesn't work in this file so cerr is sometimes used like below
+      //cerr << "tran to " << WRITE << " from " << m_state(j) << " failed" << endl;
+    }
+  }
+}
+
 void RegisterState::reset(int i)
 {
   if (i < 0) {