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ddr3.vhd 14.41 KiB
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--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_ddr3_uphy_4g_800_master_lib;
library ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
library IEEE, common_lib, technology_lib, dp_lib, tech_ddr_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
use work.ddr3_pkg.all;
entity ddr3 is
generic(
g_phy : natural := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
g_ddr : t_c_ddr3_phy;
g_mts : natural := 800; -- Megatransfers per second
g_wr_data_w : natural := c_ddr3_ctlr_data_w;
g_wr_use_ctrl : boolean := false; -- TRUE to allow filling the WR FIFO (by disabling flush) after an EOP
g_wr_fifo_depth : natural := 128; -- >=16 AND >c_ddr3_ctlr_maxburstsize , defined at read side of write FIFO.
g_rd_fifo_depth : natural := 256; -- >=16 AND >c_ddr3_ctlr_maxburstsize > c_ddr3_ctrl_nof_latent_reads, defined at write side of read FIFO.
g_rd_data_w : natural := c_ddr3_ctlr_data_w;
g_flush_wr_fifo : boolean := false; -- TRUE instantiates a dp_flush + controller to flush the write fifo when the driver is not ready to write
g_flush_ext_ena : boolean := false; -- TRUE enables the external flush_ena signal and discards flushing when driver is not ready. FALSE enables flushing when driver is not ready
g_flush_sop : boolean := false; -- When FALSE, flushing is stopped by valid data. When TRUE flushing is stopped by SOP
g_flush_sop_sync : boolean := false; -- When TRUE, flushing is stopped by receiving SOP and SYNC
g_flush_sop_channel : boolean := false; -- WHEN TRUE, flushing is stopped by receiving SOP and specified channel.
g_flush_sop_start_channel : natural := 0;
g_flush_nof_channels : natural := 0
);
port (
-- MM clock + reset
mm_rst : in std_logic := '0';
mm_clk : in std_logic := '0';
ctlr_ref_clk : in std_logic;
ctlr_rst : in std_logic; -- asynchronous reset input to controller
ctlr_gen_clk : out std_logic; -- Controller generated clock
ctlr_gen_rst : out std_logic;
ctlr_gen_clk_2x : out std_logic; -- Controller generated double frequency clock
ctlr_gen_rst_2x : out std_logic; -- ctlr_gen_rst synchronized to ctlr_gen_clk_2x
ctlr_init_done : out std_logic;
ctlr_rdy : out std_logic;