mms_io_ddr.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_select_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
use dp_lib.dp_stream_pkg.all;

entity mms_io_ddr is
  generic(
    g_sim_model               : boolean := false;
    g_technology              : natural := c_tech_select_default;
    g_tech_ddr                : t_c_tech_ddr;
    g_wr_data_w               : natural := 32;
    g_wr_fifo_depth           : natural := 256;  -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
    g_rd_fifo_depth           : natural := 256;  -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
    g_rd_data_w               : natural := 32;
    g_wr_flush_mode           : string := "VAL";  -- "VAL", "SOP", "SYN"
    g_wr_flush_use_channel    : boolean := false;
    g_wr_flush_start_channel  : natural := 0;
    g_wr_flush_nof_channels   : positive := 1
  );
  port (
    -- DDR reference clock
    ctlr_ref_clk        : in    std_logic;
    ctlr_ref_rst        : in    std_logic;

    -- DDR controller clock domain
    ctlr_clk_out        : out   std_logic;
    ctlr_rst_out        : out   std_logic;

    ctlr_clk_in         : in    std_logic;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
    ctlr_rst_in         : in    std_logic;  -- connect ctlr_rst_out to ctlr_rst_in at top level

    -- MM clock + reset
    mm_rst              : in    std_logic := '1';
    mm_clk              : in    std_logic := '0';

    -- MM interface
    reg_io_ddr_mosi     : in    t_mem_mosi := c_mem_mosi_rst;  -- register for DDR controller status info
    reg_io_ddr_miso     : out   t_mem_miso;

    -- Write FIFO clock domain
    wr_clk              : in    std_logic;
    wr_rst              : in    std_logic;

    wr_fifo_usedw       : out   std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0);  -- for monitoring purposes
    wr_sosi             : in    t_dp_sosi;