L2SDP-367, add points for signal input sample delay.

src/periph/fpga.cpp

@@ -60,7+60,7 @@
 
 Periph_fpga::Periph_fpga(string ipaddr, string expected_design_name, uint expected_firmware_version, bool enabled):
     Enabled(enabled),
     my_expected_design_name(expected_design_name),
     my_expected_firmware_version(expected_firmware_version),
     my_current_design_name("-"),
     my_current_status("offline"),
@@ -140,7+140,7 @@
     registerMap->add_register("fpga/jesd204b_csr_dev_syncn",                 "-", 1, 12, "RO", REG_FORMAT_UINT32);
     registerMap->add_register("fpga/jesd204b_csr_rx_err0",                   "-", 1, 12, "RO", REG_FORMAT_UINT32);
     registerMap->add_register("fpga/jesd204b_csr_rx_err1",                   "-", 1, 12, "RO", REG_FORMAT_UINT32);
+    
+    registerMap->add_register("fpga/signal_input_samples_delay",             "-", 1, 12, "RW", REG_FORMAT_UINT32);
 
     registerMap->print_screen();
 
@@ -475,6 +477,9 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
         else if (addr == "fpga/jesd204b_csr_rx_err0") {
             retval = read_jesd204b_csr_rx_err1(termout, format, R_MEM);
         }
+        else if (addr == "fpga/signal_input_samples_delay") {
+            retval = read_signal_input_samples_delay(termout, format);
+        }
         else {
             throw runtime_error("address " + addr + " not found!");
         }
@@ -575,6 +580,9 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ
         else if (addr == "fpga/wg_frequency") {
             retval = write_wg_frequency(data_ptr, nvalues);
         }
+        else if (addr == "fpga/signal_input_samples_delay") {
+            retval = write_signal_input_samples_delay(data_ptr, nvalues);
+        }
         else {
             throw runtime_error("address " + addr + " not found!");
         }
@@ -582,7 +590,7 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ
     return retval;
 }
 
-bool Periph_fpga::monitor(TermOutput& termout, uint seconds)
+bool Periph_fpga::monitor(TermOutput& termout)
 {
     if (!Enabled) { return false; }
     // use tictoc, tic(start) toc(stop) to see how long this function takes
@@ -594,10 +602,10 @@ bool Periph_fpga::monitor(TermOutput& termout, uint seconds)
     read_bsn_monitor_input_nof_packets(termout, REG_FORMAT_INT32, R_UCP);
     read_bsn_monitor_input_nof_valid(termout, REG_FORMAT_INT32, R_UCP);
     read_bsn_monitor_input_nof_err(termout, REG_FORMAT_INT32, R_UCP);
-    read_jesd204b_csr_rbd_count(termout, REG_FORMAT_INT32, R_UCP);
-    read_jesd204b_csr_dev_syncn(termout, REG_FORMAT_INT32, R_UCP);
-    read_jesd204b_csr_rx_err0(termout, REG_FORMAT_INT32, R_UCP);
-    read_jesd204b_csr_rx_err1(termout, REG_FORMAT_INT32, R_UCP);
+    read_jesd204b_csr_rbd_count(termout, REG_FORMAT_UINT32, R_UCP);
+    read_jesd204b_csr_dev_syncn(termout, REG_FORMAT_UINT32, R_UCP);
+    read_jesd204b_csr_rx_err0(termout, REG_FORMAT_UINT32, R_UCP);
+    read_jesd204b_csr_rx_err1(termout, REG_FORMAT_UINT32, R_UCP);
 
     termout.clear();
     tictoc.toc();
@@ -1722,6 +1730,46 @@ bool Periph_fpga::read_jesd204b_csr_rx_err1(TermOutput& termout, int format, int
     return retval;
 }
 
+bool Periph_fpga::write_signal_input_samples_delay(uint32_t *data, uint32_t nvalues) {
+    bool retval = true;
+    uint32_t *reg = new uint32_t[2];
+    uint32_t min_sample_delay = 0;
+    uint32_t max_sample_delay = 4095;
+    uint32_t sample_delay;
+    string regname;
+    uint32_t *_ptr = (uint32_t *)data;
+    for (uint i=0; i< C_S_pn; i++) {
+        sample_delay = *_ptr;
+        if ((sample_delay < min_sample_delay) || (sample_delay > max_sample_delay)) {
+            cerr << "signal_input_sample_delay not in range<" << min_sample_delay << ":" << max_sample_delay << ">" << endl;
+            retval = false;
+        } else {
+            regname = "mm/0/REG_DP_SHIFTRAM/" + to_string(i) + "/shift";
+            reg[0] = (uint32_t)sample_delay;
+            retval = Write(regname, 1, reg);
+            _ptr++;
+        }
+    }
+    delete[] reg;
+    return retval;
+}
+
+bool Periph_fpga::read_signal_input_samples_delay(TermOutput& termout, int format) {
+    bool retval = true;
+    uint32_t data[20];
+    memset((void *)data, 0, sizeof(data));
+    uint32_t *_ptr = (uint32_t *)termout.val;
+    string regname;
+    for (uint i=0; i< C_S_pn; i++) {
+        regname = "mm/0/REG_DP_SHIFTRAM/" + to_string(i) + "/shift";
+        retval = Read(regname, data);
+        *_ptr = (uint32_t)data[0];
+        _ptr++;
+    }
+    termout.nof_vals = C_S_pn;
+    termout.datatype = format;
+    return retval;
+}
 
 bool Periph_fpga::write_wdi_override(TermOutput& termout)
 {