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Commit 7a317a7d authored by Pieter Donker's avatar Pieter Donker
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Merge branch 'L2SDP-489' into 'master' 

Resolve L2SDP-489

Closes L2SDP-489

See merge request !28
parents dd7e9b0c 57d8b201
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1 merge request!28Resolve L2SDP-489
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src/constants.h
+ 2
− 0
View file @ 7a317a7d
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#define C_S_pn 12 #define C_S_pn 12
#define C_W_adc 14 #define C_W_adc 14
#define C_F_adc 200E6 #define C_F_adc 200E6
#define C_T_adc (1 / C_F_adc)
#define C_WG_MODE_OFF 0 #define C_WG_MODE_OFF 0
#define C_WG_MODE_CALC 1 #define C_WG_MODE_CALC 1
...@@ -49,6 +50,7 @@ ...@@ -49,6 +50,7 @@
#define C_N_step 1 #define C_N_step 1
#define C_N_crosslets_max 7 #define C_N_crosslets_max 7
#define C_N_scrap 512 // Number of 32 bit words in FPGA scrap memory. #define C_N_scrap 512 // Number of 32 bit words in FPGA scrap memory.
#define C_N_fft 1024 // The FFT size defines the number of samples per block.
#define C_N_pol 2 // Number of antenna polarizations, X and Y. #define C_N_pol 2 // Number of antenna polarizations, X and Y.
#define C_A_pn 6 // Number of dual polarization antennas per Processing Node (PN) FPGA. #define C_A_pn 6 // Number of dual polarization antennas per Processing Node (PN) FPGA.
// #define C_N_beamlets 976 // Number of beamlets per antenna band 488, 976 // #define C_N_beamlets 976 // Number of beamlets per antenna band 488, 976
......
src/fpga.cpp
+ 4
− 0
View file @ 7a317a7d
...@@ -89,12 +89,16 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets): ...@@ -89,12 +89,16 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets):
pointMap->add_register("FPGA_xst_processing_enable_RW", "fpga/xst_processing_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_xst_processing_enable_RW", "fpga/xst_processing_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_xst_offload_enable_R", "fpga/xst_offload_enable", nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_xst_offload_enable_R", "fpga/xst_offload_enable", nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_xst_offload_enable_RW", "fpga/xst_offload_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_xst_offload_enable_RW", "fpga/xst_offload_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_xst_offload_nof_crosslets_R", "fpga/xst_offload_nof_crosslets", nodes.size(), 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_offload_nof_crosslets_RW", "fpga/xst_offload_nof_crosslets", nodes.size(), 1, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_offload_hdr_eth_destination_mac_R", "fpga/xst_offload_hdr_eth_destination_mac", nodes.size(), 1, "RO", REG_FORMAT_STRING); pointMap->add_register("FPGA_xst_offload_hdr_eth_destination_mac_R", "fpga/xst_offload_hdr_eth_destination_mac", nodes.size(), 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_xst_offload_hdr_eth_destination_mac_RW", "fpga/xst_offload_hdr_eth_destination_mac", nodes.size(), 1, "RW", REG_FORMAT_STRING); pointMap->add_register("FPGA_xst_offload_hdr_eth_destination_mac_RW", "fpga/xst_offload_hdr_eth_destination_mac", nodes.size(), 1, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_xst_offload_hdr_ip_destination_address_R", "fpga/xst_offload_hdr_ip_destination_address", nodes.size(), 1, "RO", REG_FORMAT_STRING); pointMap->add_register("FPGA_xst_offload_hdr_ip_destination_address_R", "fpga/xst_offload_hdr_ip_destination_address", nodes.size(), 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_xst_offload_hdr_ip_destination_address_RW", "fpga/xst_offload_hdr_ip_destination_address", nodes.size(), 1, "RW", REG_FORMAT_STRING); pointMap->add_register("FPGA_xst_offload_hdr_ip_destination_address_RW", "fpga/xst_offload_hdr_ip_destination_address", nodes.size(), 1, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_xst_offload_hdr_udp_destination_port_R", "fpga/xst_offload_hdr_udp_destination_port", nodes.size(), 1, "RO", REG_FORMAT_UINT16); pointMap->add_register("FPGA_xst_offload_hdr_udp_destination_port_R", "fpga/xst_offload_hdr_udp_destination_port", nodes.size(), 1, "RO", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_xst_offload_hdr_udp_destination_port_RW", "fpga/xst_offload_hdr_udp_destination_port", nodes.size(), 1, "RW", REG_FORMAT_UINT16); pointMap->add_register("FPGA_xst_offload_hdr_udp_destination_port_RW", "fpga/xst_offload_hdr_udp_destination_port", nodes.size(), 1, "RW", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_xst_input_bsn_at_sync_R", "fpga/xst_input_sync_at_bsn", nodes.size(), 1, "RO", REG_FORMAT_INT64);
pointMap->add_register("FPGA_xst_output_sync_bsn_R", "fpga/xst_output_sync_bsn", nodes.size(), 1, "RO", REG_FORMAT_INT64);
pointMap->add_register("FPGA_processing_enable_R", "fpga/processing_enable", nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_processing_enable_R", "fpga/processing_enable", nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_processing_enable_RW", "fpga/processing_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_processing_enable_RW", "fpga/processing_enable", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
......
src/periph/fpga.cpp
+ 91
− 31
View file @ 7a317a7d
...@@ -68,6 +68,8 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets): ...@@ -68,6 +68,8 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets):
my_current_fw_version("-.-"), my_current_fw_version("-.-"),
my_bsn_input_sync_timeout(false), my_bsn_input_sync_timeout(false),
my_bsn_input_bsn(0), my_bsn_input_bsn(0),
my_xst_input_bsn_at_sync(0),
my_xst_output_sync_bsn(0),
my_bsn_input_nof_packets(0), my_bsn_input_nof_packets(0),
my_bsn_input_nof_valid(0), my_bsn_input_nof_valid(0),
my_bsn_input_nof_err(0), my_bsn_input_nof_err(0),
...@@ -75,7 +77,6 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets): ...@@ -75,7 +77,6 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets):
my_jesd_csr_dev_syncn {0}, my_jesd_csr_dev_syncn {0},
my_jesd_rx_err0 {0}, my_jesd_rx_err0 {0},
my_jesd_rx_err1 {0}, my_jesd_rx_err1 {0},
my_xst_processing_enable(false),
my_pps_offset_cnt(0), my_pps_offset_cnt(0),
my_signal_input_mean {0.0}, my_signal_input_mean {0.0},
my_signal_input_rms {0.0} my_signal_input_rms {0.0}
...@@ -210,6 +211,9 @@ bool Periph_fpga::read(TermOutput& termout, const string addr, ...@@ -210,6 +211,9 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
else if (addr == "fpga/xst_offload_enable") { else if (addr == "fpga/xst_offload_enable") {
retval = read_mm_port(termout, "REG_STAT_ENABLE_XST", "enable", format); retval = read_mm_port(termout, "REG_STAT_ENABLE_XST", "enable", format);
} }
else if (addr == "fpga/xst_offload_nof_crosslets") {
retval = read_mm_port(termout, "REG_NOF_CROSSLETS", "nof_crosslets", format);
}
else if (addr == "fpga/xst_offload_hdr_eth_destination_mac") { else if (addr == "fpga/xst_offload_hdr_eth_destination_mac") {
retval = read_xst_offload_hdr_eth_destination_mac(termout, format); retval = read_xst_offload_hdr_eth_destination_mac(termout, format);
} }
...@@ -228,6 +232,12 @@ bool Periph_fpga::read(TermOutput& termout, const string addr, ...@@ -228,6 +232,12 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
else if (addr == "fpga/xst_subband_select") { else if (addr == "fpga/xst_subband_select") {
retval = read_xst_subband_select(termout, format); retval = read_xst_subband_select(termout, format);
} }
else if (addr == "fpga/xst_input_sync_at_bsn") {
retval = read_xst_input_sync_at_bsn(termout, format, R_MEM);
}
else if (addr == "fpga/xst_output_sync_bsn") {
retval = read_xst_output_sync_bsn(termout, format, R_MEM);
}
else if (addr == "fpga/processing_enable") { else if (addr == "fpga/processing_enable") {
retval = read_mm_port(termout, "REG_BSN_SOURCE_V2", "dp_on", format); retval = read_mm_port(termout, "REG_BSN_SOURCE_V2", "dp_on", format);
} }
...@@ -414,6 +424,9 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ ...@@ -414,6 +424,9 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ
else if (addr == "fpga/xst_offload_enable") { else if (addr == "fpga/xst_offload_enable") {
retval = write_xst_offload_enable(data); retval = write_xst_offload_enable(data);
} }
else if (addr == "fpga/xst_offload_nof_crosslets") {
retval = write_xst_offload_nof_crosslets(data);
}
else if (addr == "fpga/xst_offload_hdr_eth_destination_mac") { else if (addr == "fpga/xst_offload_hdr_eth_destination_mac") {
retval = write_xst_offload_hdr_eth_destination_mac(data); retval = write_xst_offload_hdr_eth_destination_mac(data);
} }
...@@ -483,6 +496,8 @@ bool Periph_fpga::monitor(TermOutput& termout) ...@@ -483,6 +496,8 @@ bool Periph_fpga::monitor(TermOutput& termout)
read_time_since_last_pps(termout, REG_FORMAT_INT64, R_UCP); read_time_since_last_pps(termout, REG_FORMAT_INT64, R_UCP);
read_bsn_monitor_input_sync_timeout(termout, REG_FORMAT_INT64, R_UCP); read_bsn_monitor_input_sync_timeout(termout, REG_FORMAT_INT64, R_UCP);
read_bsn_monitor_input_bsn(termout, REG_FORMAT_INT64, R_UCP); read_bsn_monitor_input_bsn(termout, REG_FORMAT_INT64, R_UCP);
read_xst_input_sync_at_bsn(termout, REG_FORMAT_INT64, R_UCP);
read_xst_output_sync_bsn(termout, REG_FORMAT_INT64, R_UCP);
read_bsn_monitor_input_nof_packets(termout, REG_FORMAT_INT32, R_UCP); read_bsn_monitor_input_nof_packets(termout, REG_FORMAT_INT32, R_UCP);
read_bsn_monitor_input_nof_valid(termout, REG_FORMAT_INT32, R_UCP); read_bsn_monitor_input_nof_valid(termout, REG_FORMAT_INT32, R_UCP);
read_bsn_monitor_input_nof_err(termout, REG_FORMAT_INT32, R_UCP); read_bsn_monitor_input_nof_err(termout, REG_FORMAT_INT32, R_UCP);
...@@ -1292,6 +1307,11 @@ bool Periph_fpga::write_xst_offload_enable(const char *data) ...@@ -1292,6 +1307,11 @@ bool Periph_fpga::write_xst_offload_enable(const char *data)
return Write("mm/0/REG_STAT_ENABLE_XST/0/enable", _data); return Write("mm/0/REG_STAT_ENABLE_XST/0/enable", _data);
} }
bool Periph_fpga::write_xst_offload_nof_crosslets(const char *data)
{
uint32_t *_ptr = (uint32_t *)data;
return Write("mm/0/REG_NOF_CROSSLETS/0/nof_crosslets", _ptr);
}
bool Periph_fpga::read_xst_offload_hdr_eth_destination_mac(TermOutput& termout, int format) bool Periph_fpga::read_xst_offload_hdr_eth_destination_mac(TermOutput& termout, int format)
{ {
...@@ -1398,13 +1418,12 @@ bool Periph_fpga::read_xst_processing_enable(TermOutput& termout, int format) ...@@ -1398,13 +1418,12 @@ bool Periph_fpga::read_xst_processing_enable(TermOutput& termout, int format)
{ {
bool retval = true; bool retval = true;
// uint32_t data[20]; uint32_t data[1];
// memset((void *)data, 0, sizeof(data)); memset((void *)data, 0, sizeof(data));
// retval = Read("mm/0/REG_BSN_SCHEDULER_XSUB/0/enable", data); retval = Read("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_output_enable", data);
// bool processing_enable = (bool)data[0];
bool *_ptr = (bool *)termout.val; bool *_ptr = (bool *)termout.val;
*_ptr = my_xst_processing_enable; *_ptr = (bool)data[0];;
termout.nof_vals = 1; termout.nof_vals = 1;
termout.datatype = format; termout.datatype = format;
return retval; return retval;
...@@ -1415,38 +1434,41 @@ bool Periph_fpga::write_xst_processing_enable(const char *data) ...@@ -1415,38 +1434,41 @@ bool Periph_fpga::write_xst_processing_enable(const char *data)
bool retval = true; bool retval = true;
uint32_t *reg = new uint32_t[2]; uint32_t *reg = new uint32_t[2];
bool processing_enable = (bool)data[0]; bool processing_enable = (bool)data[0];
uint64_t scheduled_bsn; uint64_t start_bsn;
if (processing_enable == true) { if (processing_enable == true) {
// get bsn and add latency // get bsn and add latency
retval &= Read("mm/0/REG_BSN_SCHEDULER_XSUB/0/scheduled_bsn", reg); retval &= Read("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_input_bsn_at_sync", reg);
if (retval == true) { if (retval == true) {
scheduled_bsn = (((uint64_t)reg[1] << 32) + reg[0]); start_bsn = (((uint64_t)reg[1] << 32) + reg[0]);
cout << "bsn=" << to_string(scheduled_bsn) << endl; cout << "bsn=" << to_string(start_bsn) << endl;
scheduled_bsn += C_BSN_LATENCY; start_bsn = start_bsn + (2 * C_F_adc) / C_N_fft;
cout << "new bsn=" << to_string(scheduled_bsn) << endl; cout << "new bsn=" << to_string(start_bsn) << endl;
reg[0] = (uint32_t)(scheduled_bsn & 0xffffffff); reg[0] = (uint32_t)(start_bsn & 0xffffffff);
reg[1] = (uint32_t)((scheduled_bsn >> 32) & 0xffffffff); reg[1] = (uint32_t)((start_bsn >> 32) & 0xffffffff);
// write sheduled bsn // write sheduled bsn
retval &= Write("mm/0/REG_BSN_SCHEDULER_XSUB/0/scheduled_bsn", reg); retval &= Write("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_start_bsn", reg);
if (retval == true) { reg[0] = 1;
my_xst_processing_enable = processing_enable; // write ctrl_enable = 1
retval &= Write("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_enable", reg);
} }
} }
else {
reg[0] = 0;
// write ctrl_enable = 0
retval &= Write("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_enable", reg);
} }
return retval; return retval;
} }
bool Periph_fpga::read_xst_integration_interval(TermOutput& termout, int format) bool Periph_fpga::read_xst_integration_interval(TermOutput& termout, int format)
{ {
// TODO, fill in if supported in FW
bool retval = true; bool retval = true;
// uint32_t data[20]; uint32_t data[20];
// memset((void *)data, 0, sizeof(data)); memset((void *)data, 0, sizeof(data));
// retval = Read("mm/0/REG_STAT_HDR_DAT_XST/0/??", data); retval = Read("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_interval_size", data);
// double interval = ??; double interval = (double)data[0] * C_T_adc;
double interval = 1.0;
double *_ptr = (double *)termout.val; double *_ptr = (double *)termout.val;
*_ptr = interval; *_ptr = interval;
termout.nof_vals = 1; termout.nof_vals = 1;
...@@ -1456,10 +1478,10 @@ bool Periph_fpga::read_xst_integration_interval(TermOutput& termout, int format) ...@@ -1456,10 +1478,10 @@ bool Periph_fpga::read_xst_integration_interval(TermOutput& termout, int format)
bool Periph_fpga::write_xst_integration_interval(const char *data) bool Periph_fpga::write_xst_integration_interval(const char *data)
{ {
// uint32_t *_ptr = (uint32_t *)data; double *_ptr = (double *)data;
// TODO, fill in if supported in FW uint32_t *reg = new uint32_t[1];
// return Write("mm/0/REG_STAT_HDR_DAT_XST/0/??", data); reg[0] = (uint32_t)round(_ptr[0] * C_F_adc);
return true; return Write("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_interval_size", reg);
} }
bool Periph_fpga::read_xst_subband_select(TermOutput& termout, int format) bool Periph_fpga::read_xst_subband_select(TermOutput& termout, int format)
...@@ -1481,6 +1503,44 @@ bool Periph_fpga::read_xst_subband_select(TermOutput& termout, int format) ...@@ -1481,6 +1503,44 @@ bool Periph_fpga::read_xst_subband_select(TermOutput& termout, int format)
return retval; return retval;
} }
bool Periph_fpga::read_xst_input_sync_at_bsn(TermOutput& termout, int format, int mode) {
bool retval = true;
int64_t bsn = my_xst_input_bsn_at_sync;
if (mode == R_UCP) {
uint32_t data[2];
memset((void *)data, 0, sizeof(data));
string regname;
regname = "mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_input_bsn_at_sync";
retval = Read(regname, data);
bsn = (((int64_t)data[1] << 32) + data[0]);
}
int64_t *_ptr = (int64_t *)termout.val;
*_ptr = bsn;
termout.nof_vals = 1;
termout.datatype = format;
my_xst_input_bsn_at_sync = bsn;
return retval;
}
bool Periph_fpga::read_xst_output_sync_bsn(TermOutput& termout, int format, int mode) {
bool retval = true;
int64_t bsn = my_xst_output_sync_bsn;
if (mode == R_UCP) {
uint32_t data[2];
memset((void *)data, 0, sizeof(data));
string regname;
regname = "mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_output_sync_bsn";
retval = Read(regname, data);
bsn = (((int64_t)data[1] << 32) + data[0]);
}
int64_t *_ptr = (int64_t *)termout.val;
*_ptr = bsn;
termout.nof_vals = 1;
termout.datatype = format;
my_xst_output_sync_bsn = bsn;
return retval;
}
bool Periph_fpga::write_xst_subband_select(const char *data) bool Periph_fpga::write_xst_subband_select(const char *data)
{ {
uint32_t *_ptr = (uint32_t *)data; uint32_t *_ptr = (uint32_t *)data;
...@@ -1579,10 +1639,10 @@ When FPGA_wg_enable_RW is set True, then enable the WG via mode = c_mode_calc = ...@@ -1579,10 +1639,10 @@ When FPGA_wg_enable_RW is set True, then enable the WG via mode = c_mode_calc =
WG starts or restarts when it gets a trigger from the BSN scheduler. The trigger has to occur at the WG starts or restarts when it gets a trigger from the BSN scheduler. The trigger has to occur at the
same BSN for all WG that are enabled, to ensure that they start synchronously. Any WG that are not same BSN for all WG that are enabled, to ensure that they start synchronously. Any WG that are not
enabled will ignore the trigger. The exact BSN at which the WG start is don't care. The trigger is enabled will ignore the trigger. The exact BSN at which the WG start is don't care. The trigger is
scheduled via scheduled_bsn in REG_BSN_SCHEDULER. The current BSN can be read from the REG_BSN_SCHEDULER scheduled via start_bsn in REG_BSN_SCHEDULER. The current BSN can be read from the REG_BSN_SCHEDULER
on one of the FPGAs. Assume the communication to write the scheduled_bsn in all FPGAs will take on one of the FPGAs. Assume the communication to write the start_bsn in all FPGAs will take
less than 1 ms, then a margin of 10 - 100 ms is sufficient. The BSN period corresponds to 5.12 μs, so less than 1 ms, then a margin of 10 - 100 ms is sufficient. The BSN period corresponds to 5.12 μs, so
a c_bsn_latency = 20000 (≈ 100 ms) is sufficient for scheduled_bsn = current_bsn + c_bsn_latency. a c_bsn_latency = 20000 (≈ 100 ms) is sufficient for start_bsn = current_bsn + c_bsn_latency.
The MP reports False when mode = c_mode_off = 0, else True. The MP reports False when mode = c_mode_off = 0, else True.
Note: Note:
The nof_samples field and mode field share an address in REG_DIAG_WG. The nof_samples = 2**W_wg_buf = 1024. The nof_samples field and mode field share an address in REG_DIAG_WG. The nof_samples = 2**W_wg_buf = 1024.
......
src/periph/fpga.h
+ 5
− 0
View file @ 7a317a7d
...@@ -61,6 +61,8 @@ private: ...@@ -61,6 +61,8 @@ private:
bool my_bsn_input_sync_timeout; bool my_bsn_input_sync_timeout;
int64_t my_bsn_input_bsn; int64_t my_bsn_input_bsn;
int64_t my_xst_input_bsn_at_sync;
int64_t my_xst_output_sync_bsn;
int32_t my_bsn_input_nof_packets; int32_t my_bsn_input_nof_packets;
int32_t my_bsn_input_nof_valid; int32_t my_bsn_input_nof_valid;
int32_t my_bsn_input_nof_err; int32_t my_bsn_input_nof_err;
...@@ -128,11 +130,14 @@ private: ...@@ -128,11 +130,14 @@ private:
bool read_xst_subband_select(TermOutput& termout, int format); bool read_xst_subband_select(TermOutput& termout, int format);
bool write_xst_subband_select(const char *data); bool write_xst_subband_select(const char *data);
bool read_xst_input_sync_at_bsn(TermOutput& termout, int format, int mode);
bool read_xst_output_sync_bsn(TermOutput& termout, int format, int mode);
bool read_xst_integration_interval(TermOutput& termout, int format); bool read_xst_integration_interval(TermOutput& termout, int format);
bool write_xst_integration_interval(const char *data); bool write_xst_integration_interval(const char *data);
bool read_xst_processing_enable(TermOutput& termout, int format); bool read_xst_processing_enable(TermOutput& termout, int format);
bool write_xst_processing_enable(const char *data); bool write_xst_processing_enable(const char *data);
bool write_xst_offload_enable(const char *data); bool write_xst_offload_enable(const char *data);
bool write_xst_offload_nof_crosslets(const char *data);
bool read_xst_offload_hdr_eth_destination_mac(TermOutput& termout, int format); bool read_xst_offload_hdr_eth_destination_mac(TermOutput& termout, int format);
bool write_xst_offload_hdr_eth_destination_mac(const char *data); bool write_xst_offload_hdr_eth_destination_mac(const char *data);
bool read_xst_offload_hdr_ip_destination_address(TermOutput& termout, int format); bool read_xst_offload_hdr_ip_destination_address(TermOutput& termout, int format);
......
src/sdptr.cpp
+ 19
− 4
View file @ 7a317a7d
...@@ -76,7 +76,22 @@ void monitor() ...@@ -76,7 +76,22 @@ void monitor()
while (ServerRunning) { while (ServerRunning) {
struct timespec current_time_timespec;
clock_gettime(CLOCK_REALTIME, (struct timespec *)&current_time_timespec);
SD.t0.tv_sec = SD.t0.tv_sec + SD.timetick; // specify next position in time SD.t0.tv_sec = SD.t0.tv_sec + SD.timetick; // specify next position in time
if (SD.t0.tv_sec < current_time_timespec.tv_sec) {
// skip ahead if we already are beyond the next tick.
// this prevents us from trying to catch up if the host system
// was in hibernation or this process was otherwise suspended.
// this means that SD.uptime will reflect the number of seconds
// this process was actually running, and now - SD.start_time
// reflects the wall-clock time that passed since start.
time_t missed = current_time_timespec.tv_sec - SD.t0.tv_sec;
SD.uptime += (uint32_t)missed;
cerr << "!!!!! MONITOR THREAD: Missed " << missed << " seconds !!!!!" << endl;
SD.t0.tv_sec = current_time_timespec.tv_sec + SD.timetick;
}
SD.t0.tv_nsec = 10000000L; // 0..999999999 // offset 10ms in a new second SD.t0.tv_nsec = 10000000L; // 0..999999999 // offset 10ms in a new second
pthread_mutex_lock(&SD.newpoint_lock); pthread_mutex_lock(&SD.newpoint_lock);
pthread_cond_timedwait(&SD.newpoint_cond, &SD.newpoint_lock, (const struct timespec *)&SD.t0); pthread_cond_timedwait(&SD.newpoint_cond, &SD.newpoint_lock, (const struct timespec *)&SD.t0);
......
src/tools/mmap.cpp
+ 5
− 5
View file @ 7a317a7d
...@@ -42,7 +42,7 @@ typedef struct { ...@@ -42,7 +42,7 @@ typedef struct {
string field_name; string field_name;
uint32_t base_addr; // in MM words uint32_t base_addr; // in MM words
uint32_t n_fields; uint32_t n_fields;
string acces_mode; string access_mode;
string radix; string radix;
uint32_t mm_mask; uint32_t mm_mask;
uint32_t user_mask; uint32_t user_mask;
...@@ -78,7 +78,7 @@ void mmap_add_register(CMMap& regmap, mm_info_t mm_info) ...@@ -78,7 +78,7 @@ void mmap_add_register(CMMap& regmap, mm_info_t mm_info)
mm_info.mm_mask, mm_info.mm_mask,
mm_info.shift, mm_info.shift,
mm_info.n_fields, mm_info.n_fields,
mm_info.acces_mode, mm_info.access_mode,
mm_info.radix, mm_info.radix,
mm_info.port_type, mm_info.port_type,
mm_info.peripheral_span, mm_info.peripheral_span,
...@@ -93,7 +93,7 @@ void mmap_add_register(CMMap& regmap, mm_info_t mm_info) ...@@ -93,7 +93,7 @@ void mmap_add_register(CMMap& regmap, mm_info_t mm_info)
mm_info.mm_mask, mm_info.mm_mask,
mm_info.shift, mm_info.shift,
mm_info.n_fields, mm_info.n_fields,
mm_info.acces_mode, mm_info.access_mode,
mm_info.radix, mm_info.radix,
mm_info.port_type, mm_info.port_type,
mm_info.peripheral_span, mm_info.peripheral_span,
...@@ -177,9 +177,9 @@ CMMap mmap_to_regmap(istringstream& iss) ...@@ -177,9 +177,9 @@ CMMap mmap_to_regmap(istringstream& iss)
mm_info.n_fields = stoi(val_str); mm_info.n_fields = stoi(val_str);
} }
strs >> val_str; // get acces_mode strs >> val_str; // get access_mode
if (val_str != "-") { if (val_str != "-") {
mm_info.acces_mode = val_str; mm_info.access_mode = val_str;
} }
strs >> val_str; // get radix strs >> val_str; // get radix
......
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