Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
P
python_test_scripts
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
LOFAR2.0
python_test_scripts
Commits
d96bc365
Commit
d96bc365
authored
Jun 19, 2021
by
Paulus Kruger
Browse files
Options
Downloads
Patches
Plain Diff
Added Read-out registers
parent
578e1525
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
APSCT_CLK_I2C.py
+52
-13
52 additions, 13 deletions
APSCT_CLK_I2C.py
with
52 additions
and
13 deletions
APSCT_CLK_I2C.py
+
52
−
13
View file @
d96bc365
...
...
@@ -24,14 +24,15 @@ else:
from
I2C_serial
import
*
DEBUG
=
False
I2CBUSNR
=
3
sleep_time
=
0.
0
5
I2CBUSNR
=
5
sleep_time
=
0.
1
5
SET_PLL
=
True
READ_LOCK
=
True
READ_ALL
=
False
CHECK_EEPROM
=
Tru
e
PWR_RST
=
False
READ_LOCK
=
False
#
True
READ_ALL
=
True
#
False
CHECK_EEPROM
=
Fals
e
PWR_RST
=
True
#
False
READ_SENSOR
=
True
READ_REGS
=
False
#True
CLK_FREQ
=
'
200MHz
'
dev_i2c_eeprom
=
I2C
(
0x50
)
...
...
@@ -51,7 +52,7 @@ def Write_byte_PLL(reg_address, wr_data, ADDRESS=0x20):
#
I2C_device
=
I2C
(
ADDRESS
,
BUSNR
=
I2CBUSNR
)
PLL_rw
=
0x00
# 0 for write, 1 for read
stri
=
"
Write : 0x{
0
:{fill}2x}
to Address :
0x{
1
:{fill}2x}
"
.
format
(
wr_data
,
reg_address
,
fill
=
'
0
'
)
stri
=
"
Write
to address
: 0x{
1
:{fill}2x}
value
0x{
0
:{fill}2x}
"
.
format
(
wr_data
,
reg_address
,
fill
=
'
0
'
)
print
(
stri
)
I2C_device
.
write_bytes
(
0x06
,
0x2C
)
if
DEBUG
:
...
...
@@ -90,13 +91,12 @@ def Read_byte_PLL(reg_address, nof_bytes=1, ADDRESS=0x20 ):
I2C_device
.
write_bytes
(
0x06
,
0x2C
)
data
=
(
reg_address
<<
7
)
+
PLL_rw
bit_array
=
"
{0:{fill}8b}
"
.
format
(
data
,
fill
=
'
0
'
)
for
bit
in
bit_array
:
for
clk
in
range
(
2
):
Write_data
=
0x02
|
(
0
<<
CS
)
|
(
clk
<<
SCLK
)
|
(
int
(
bit
)
<<
SDI
)
I2C_device
.
write_bytes
(
0x02
,
Write_data
)
#
sleep(sleep_time)
sleep
(
sleep_time
)
# print("read byte")
read_bit
=
''
...
...
@@ -117,6 +117,33 @@ def Read_byte_PLL(reg_address, nof_bytes=1, ADDRESS=0x20 ):
print
(
stri
)
return
read_bit
;
def
read_all_regs_pll
(
pll_frequency
=
'
200MHz
'
)
:
I2C_device
=
I2C
(
0x20
,
BUSNR
=
I2CBUSNR
)
#clock selection
I2C_device
.
write_bytes
(
0x07
,
0x00
)
if
pll_frequency
==
'
160MHz
'
:
print
(
"
Read PLL 160 MHz
"
)
pll_address
=
PLL_160M
# I2C_device.write_bytes(0x03, 0x0F)
else
:
print
(
"
Read PLL 200 MHz
"
)
pll_address
=
PLL_200M
# I2C_device.write_bytes(0x03, 0xF8)
# for reg_cnt in range(0x15):
bytes_to_read
=
24
ret_value
=
Read_byte_PLL
(
0
,
nof_bytes
=
bytes_to_read
,
ADDRESS
=
pll_address
)
for
cnt
in
range
(
bytes_to_read
):
start
=
cnt
*
8
stri
=
"
Reg nr 0x{:0>2x} value: 0x{:0>2x}
"
.
format
(
cnt
,
int
(
ret_value
[
start
:
start
+
8
],
2
))
print
(
stri
)
def
read_IO_expanderis
():
i2c_addr
=
[
0x20
,
0x21
]
for
addr
in
i2c_addr
:
I2C_device
=
I2C
(
addr
,
BUSNR
=
I2CBUSNR
)
#clock selection
for
reg_cnt
in
range
(
8
):
ack
,
ret_value
=
I2C_device
.
read_bytes
(
reg_cnt
,
2
)
stri
=
"
Expander : 0x{:0>2x}, Reg 0x{:0>2x}, value 0x{}{}
"
.
format
(
addr
,
reg_cnt
,
ret_value
[
0
],
ret_value
[
1
])
#[start+2:start])
print
(
stri
)
def
setup_pll
(
pll_frequency
=
'
200MHz
'
)
:
I2C_device
=
I2C
(
0x20
,
BUSNR
=
I2CBUSNR
)
#clock selection
...
...
@@ -124,13 +151,13 @@ def setup_pll(pll_frequency='200MHz') :
if
pll_frequency
==
'
160MHz
'
:
print
(
"
Set PLL to 160 MHz mode
"
)
pll_address
=
PLL_160M
I2C_device
.
write_bytes
(
0x03
,
0x0
8
)
I2C_device
.
write_bytes
(
0x03
,
0x0
F
)
else
:
print
(
"
Set PLL to 200 MHz mode
"
)
pll_address
=
PLL_200M
I2C_device
.
write_bytes
(
0x03
,
0xF
8
)
I2C_device
.
write_bytes
(
0x03
,
0xF
F
)
Write_byte_PLL
(
0x03
,
0x08
,
pll_address
)
Write_byte_PLL
(
0x04
,
0x
CF
,
pll_address
)
# CF disable not used outputs, 00 enable all
Write_byte_PLL
(
0x04
,
0x
00
,
pll_address
)
# CF disable not used outputs, 00 enable all
Write_byte_PLL
(
0x05
,
0x97
,
pll_address
)
Write_byte_PLL
(
0x06
,
0x10
,
pll_address
)
# cp inv = 0xF4 other 0xE4
Write_byte_PLL
(
0x07
,
0x04
,
pll_address
)
# Divider R = 1 dec
...
...
@@ -142,6 +169,7 @@ def setup_pll(pll_frequency='200MHz') :
else
:
Write_byte_PLL
(
0x0A
,
0x14
,
pll_address
)
Write_byte_PLL
(
0x09
,
0x00
,
pll_address
)
Write_byte_PLL
(
0x0C
,
0x80
,
pll_address
)
Write_byte_PLL
(
0x0D
,
0x01
,
pll_address
)
# Dig CLK = 200/1 = 200 MHz
Write_byte_PLL
(
0x0F
,
0x01
,
pll_address
)
# RCU CLK = 200/1 = 200 MHz
Write_byte_PLL
(
0x11
,
0x01
,
pll_address
)
# PPS ref CLK = 200/1 = 200 MHz
...
...
@@ -149,6 +177,8 @@ def setup_pll(pll_frequency='200MHz') :
def
power
(
state
):
stri
=
"
Power to {}
"
.
format
(
state
)
print
(
stri
)
I2C_IO_device_A
=
I2C
(
0x20
,
BUSNR
=
I2CBUSNR
)
I2C_IO_device_A
.
write_bytes
(
0x06
,
0x2C
)
# '0' is output
I2C_IO_device_A
.
write_bytes
(
0x07
,
0x00
)
# '0' is output
...
...
@@ -218,7 +248,7 @@ def read_voltage(input_channel=0):
if
DEBUG
:
stri
=
"
Word to select sens input is 0x{0:x}
"
.
format
(
channel_select_word
)
print
(
stri
)
sleep
(
0.
5
)
sleep
(
0.
1
)
I2C_device
.
write_bytes
(
channel_select_word
,
0xB8
)
sleep
(
0.5
)
ret_ack
,
ret_value
=
I2C_device
.
read_last_reg
(
3
)
...
...
@@ -257,6 +287,8 @@ def read_temp():
else
:
print
(
"
Error reading tempeature
"
)
#if READ_REGS:
# read_all_regs_pll(CLK_FREQ)
if
CHECK_EEPROM
:
wr_rd_eeprom
()
...
...
@@ -283,5 +315,12 @@ if READ_LOCK:
else
:
print
(
"
Not locked --> PLL Error
"
)
if
READ_REGS
:
read_all_regs_pll
(
CLK_FREQ
)
if
READ_ALL
:
read_all_regs_pll
(
CLK_FREQ
)
read_IO_expanderis
()
if
READ_SENSOR
:
apsct_sensors
()
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment