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LOFAR2.0
python_test_scripts
Commits
c2d40fc8
Commit
c2d40fc8
authored
Feb 13, 2023
by
GijsSchoonderbeek
Browse files
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Plain Diff
Update default resisters write to AD9511
parent
362b52b3
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No related tags found
1 merge request
!6
Apsct ad9511
Changes
1
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1 changed file
apsct_lib.py
+32
-27
32 additions, 27 deletions
apsct_lib.py
with
32 additions
and
27 deletions
apsct_lib.py
+
32
−
27
View file @
c2d40fc8
...
...
@@ -155,8 +155,9 @@ class PllClass:
if
DEBUG
:
stri
=
"
IO expander wrote 0x{0:x}, read 0x{1}
"
.
format
(
0x2C
,
rd_bytes
[
1
])
print
(
stri
)
data
=
(
reg_address
<<
9
)
+
(
pll_rw
<<
8
)
+
wr_data
bit_array
=
"
{0:{fill}16b}
"
.
format
(
data
,
fill
=
'
0
'
)
nof_bytes
=
1
data
=
(
pll_rw
<<
23
)
+
(
nof_bytes
<<
21
)
+
(
reg_address
<<
8
)
+
wr_data
bit_array
=
"
{0:{fill}24b}
"
.
format
(
data
,
fill
=
'
0
'
)
self
.
dev_i2c_pll
.
write_bytes
(
0x02
,
0x02
|
(
0x1
<<
APSCT_I2C
.
CS
))
for
bit
in
bit_array
:
for
clk
in
range
(
2
):
...
...
@@ -178,8 +179,8 @@ class PllClass:
#
pll_rw
=
0x01
# 0 for write, 1 for read
self
.
dev_i2c_pll
.
write_bytes
(
0x06
,
0x2C
)
data
=
(
reg_addres
s
<<
7
)
+
pll_rw
bit_array
=
"
{0:{fill}
8
b}
"
.
format
(
data
,
fill
=
'
0
'
)
data
=
(
pll_rw
<<
15
)
+
(
nof_byte
s
<<
13
)
+
reg_address
bit_array
=
"
{0:{fill}
16
b}
"
.
format
(
data
,
fill
=
'
0
'
)
for
bit
in
bit_array
:
for
clk
in
range
(
2
):
write_data
=
0x02
|
(
0
<<
APSCT_I2C
.
CS
)
|
(
clk
<<
APSCT_I2C
.
SCLK
)
|
(
int
(
bit
)
<<
APSCT_I2C
.
SDI
)
...
...
@@ -208,41 +209,45 @@ class PllClass:
# Set registers on the PLL
#
print
(
f
"
Setup PPL
{
self
.
frequency
}
"
)
self
.
dev_i2c_pll
.
write_bytes
(
0x07
,
0x00
)
divider_r
=
1
divider_a
=
0
divider_p
=
2
divider_b
=
(
self
.
frequency
*
divider_r
)
/
(
10
*
divider_p
)
charge_pump_current
=
3
# 0 is low (0.6 mA), 7 is high (4.8 mA)
if
self
.
frequency
==
'
160MHz
'
:
i2c_address
=
APSCT_I2C
.
PLL_200M
dev_i2c_pll_sel
=
I2C
(
i2c_address
,
BUSNR
=
I2CBUSNR
)
dev_i2c_pll_sel
.
write_bytes
(
0x03
,
0x08
)
else
:
self
.
dev_i2c_pll
.
write_bytes
(
0x03
,
0x28
)
self
.
write_byte_pll
(
0x0
3
,
0x0C
)
s
leep
(
0.5
)
self
.
write_byte_pll
(
0x0
3
,
0x08
)
self
.
write_byte_pll
(
0x0
3
,
0x0
8
)
self
.
write_byte_pll
(
0x0
4
,
0x
CF
)
# C
F disable not used outputs, 00 enable all
self
.
write_byte_pll
(
0x0
5
,
0x
9
7
)
self
.
write_byte_pll
(
0x0
6
,
0x
1
0
)
#
cp inv = 0xF4 other 0xE4
self
.
write_byte_pll
(
0x0
7
,
0x0
4
)
# Divider R = 1 dec
self
.
write_byte_pll
(
0x
08
,
0x0
1
)
self
.
write_byte_pll
(
0x
07
,
0x0
0
)
self
.
write_byte_pll
(
0x
09
,
0x
1
0
)
#
reset
if
self
.
frequency
==
'
160MHz
'
:
self
.
write_byte_pll
(
0x0
A
,
0x
10
)
el
se
:
self
.
write_byte_pll
(
0x
0A
,
0x
14
)
self
.
write_byte_pll
(
0x
09
,
0x
0
0
)
self
.
write_byte_pll
(
0x
0C
,
0x8
F
)
self
.
write_byte_pll
(
0x
0D
,
0x8
8
)
#
Dig CLK = 200/1 = 200 MHz
self
.
write_byte_pll
(
0x
0F
,
0x
0
8
)
#
RCU CLK = 200/1 = 200 MHz
self
.
write_byte_pll
(
0x
11
,
0x0
8
)
#
PPS ref CLK = 200/1 = 200 MHz
self
.
write_byte_pll
(
0x13
,
0x88
)
# T.P. CLK = 200/1 = 200 MHz
self
.
write_byte_pll
(
0x0
4
,
(
divider_a
&
0x3F
)
)
s
elf
.
write_byte_pll
(
0x05
,
(
divider_b
&
0x1F00
)
>>
8
)
self
.
write_byte_pll
(
0x0
6
,
(
divider_b
&
0x00FF
)
)
self
.
write_byte_pll
(
0x0
7
,
0x0
4
)
# Lock detect
self
.
write_byte_pll
(
0x0
8
,
0x
03
)
# C
harge pump normal + Status bit
self
.
write_byte_pll
(
0x0
9
,
(
charge_pump_current
&
0x7
)
<<
4
)
self
.
write_byte_pll
(
0x0
A
,
0x0
4
)
#
Fixed Divide 2
self
.
write_byte_pll
(
0x0
B
,
0x0
0
)
self
.
write_byte_pll
(
0x
45
,
0x0
0
)
# CLK2 as feedback clock input
self
.
write_byte_pll
(
0x
3D
,
0x0
8
)
# OUT0 ON LVDS Standard
self
.
write_byte_pll
(
0x
3E
,
0x0
A
)
#
OUT1 OFF
self
.
write_byte_pll
(
0x3F
,
0x0A
)
# OUT2 OFF
self
.
write_byte_pll
(
0x
4
0
,
0x
03
)
# OUT3 OFF
s
el
f
.
write_byte_pll
(
0x41
,
0x02
)
# OUT4 ON LVDS Standard
self
.
write_byte_pll
(
0x
4B
,
0x
80
)
# OUT0 bypass divider
self
.
write_byte_pll
(
0x
4D
,
0x
8
0
)
# OUT1 bypass divider
self
.
write_byte_pll
(
0x
4F
,
0x8
0
)
# OUT2 bypass divider
self
.
write_byte_pll
(
0x
51
,
0x8
0
)
#
OUT3 bypass divider
self
.
write_byte_pll
(
0x
53
,
0x8
0
)
#
OUT4 bypass divider
self
.
write_byte_pll
(
0x
5A
,
0x0
1
)
#
Update registers
def
read_all_regs_pll
(
self
):
#
# Read all registers on the PLL and print on screen
#
self
.
dev_i2c_pll
.
write_bytes
(
0x07
,
0x00
)
bytes_to_read
=
2
4
bytes_to_read
=
1
2
ret_value
=
self
.
read_byte_pll
(
0
,
nof_bytes
=
bytes_to_read
)
for
cnt
in
range
(
bytes_to_read
):
start
=
cnt
*
8
...
...
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