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Commit bf6c2e04 authored by Gijs Schoonderbeek's avatar Gijs Schoonderbeek
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update after first test on HW

parent 71ffa39f
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......@@ -108,7 +108,7 @@ def Read_byte_PLL(reg_address, nof_bytes=1, ADDRESS=0x20 ):
def setup_pll(pll_frequency='200MHz') :
# Check PLL is in lock
if pll_frequency = '160MHz':
if pll_frequency == '160MHz':
pll_address = PLL_160M
else:
pll_address=PLL_200M
......
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