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production_apsct.py

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    mpu_armv8.h 10.99 KiB
    /******************************************************************************
     * @file     mpu_armv8.h
     * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
     * @version  V5.1.0
     * @date     08. March 2019
     ******************************************************************************/
    /*
     * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
     *
     * SPDX-License-Identifier: Apache-2.0
     *
     * Licensed under the Apache License, Version 2.0 (the License); you may
     * not use this file except in compliance with the License.
     * You may obtain a copy of the License at
     *
     * www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing, software
     * distributed under the License is distributed on an AS IS BASIS, WITHOUT
     * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     * See the License for the specific language governing permissions and
     * limitations under the License.
     */
    
    #if   defined ( __ICCARM__ )
      #pragma system_include         /* treat file as system include file for MISRA check */
    #elif defined (__clang__)
      #pragma clang system_header    /* treat file as system include file */
    #endif
    
    #ifndef ARM_MPU_ARMV8_H
    #define ARM_MPU_ARMV8_H
    
    /** \brief Attribute for device memory (outer only) */
    #define ARM_MPU_ATTR_DEVICE                           ( 0U )
    
    /** \brief Attribute for non-cacheable, normal memory */
    #define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
    
    /** \brief Attribute for normal memory (outer and inner)
    * \param NT Non-Transient: Set to 1 for non-transient data.
    * \param WB Write-Back: Set to 1 to use write-back update policy.
    * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
    * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
    */
    #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
      (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
    
    /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
    #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
    
    /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
    #define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
    
    /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
    #define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
    
    /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
    #define ARM_MPU_ATTR_DEVICE_GRE    (3U)
    
    /** \brief Memory Attribute
    * \param O Outer memory attributes
    * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
    */
    #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
    
    /** \brief Normal memory non-shareable  */
    #define ARM_MPU_SH_NON   (0U)
    
    /** \brief Normal memory outer shareable  */