tb_io_ddr.vhd

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--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
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-- This testbench tests the different type of DDR controllers.
--
-- The DUT can be selected, using the g_technology and g_tech_ddr constants.
--
-- Testbench is selftesting:
--
-- > as 10
-- > run -all
--
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, diagnostics_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;

entity tb_io_ddr is
  generic (
    g_sim_model             : boolean := true;  -- FALSE;
    g_technology            : natural := c_tech_select_default;
    g_tech_ddr3             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
    --g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
    g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_16g_1600m_64;
    --g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_16g_1600m_72_64;
    g_tb_end                : boolean := true;  -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
    g_cross_domain_dvr_ctlr : boolean := true;  -- when TRUE insert clock cross domain logic and also insert clock cross domain logic when g_dvr_clk_period/=c_ctlr_clk_period
    g_dvr_clk_period        : time := 5 ns;  -- 200 MHz
    g_dp_factor             : natural := 4;  -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
    g_block_len             : natural := 100;  -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
    g_nof_block             : natural := 2;  -- number of blocks that will be written to DDR and readback from DDR
    g_nof_wr_per_block      : natural := 1;  -- number of write accesses per block
    g_nof_rd_per_block      : natural := 1;  -- number of read accesses per block
    g_nof_repeat            : natural := 1;  -- number of stimuli repeats with write flush after each repeat
    g_wr_flush_mode         : string := "VAL"  -- "VAL", "SOP", "SYN"
  );
  port (
    tb_end : out std_logic
  );
end entity tb_io_ddr;

architecture str of tb_io_ddr is
  -- Select DDR3 or DDR4 dependent on the technology and sim model
  constant c_mem_ddr                  : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);