Skip to content
Snippets Groups Projects

Timestamp logs

Merged Jan David Mol requested to merge timestamp-logs into master
9 files
+ 104
87
Compare changes
  • Side-by-side
  • Inline
Files
9
+ 16
15
from I2Cdevices import *;
import numpy as np
import logging
class I2Cbitbang(I2Cdevices):
def I2CSet(self,dev,reg,value,I2Ccallback,width=8,bitoffset=0):
@@ -10,7 +11,7 @@ class I2Cbitbang(I2Cdevices):
Addr=Dev['dev_address'];
# data2=[Addr<<1,regnr]+data;
data2=[Addr<<1]+int2bytes(regnr)+value
# print(data2)
# logging.info("%s",data2)
I2Ccallback('SDO',0)
I2Ccallback('SCL',1)
if not(I2CbbTX(data2,I2Ccallback)): return False;
@@ -18,9 +19,9 @@ class I2Cbitbang(I2Cdevices):
data3=[0]
if not(I2CbbRX(data2,data3,I2Ccallback)): return False;
if data3[0]!=0x80:
print("Expected Ack 0x80, received:",data3);
logging.error("Expected Ack 0x80, received: %s",data3);
return False;
print("Si4012 TX success!")
logging.info("Si4012 TX success!")
return True;
def I2CGet(self,dev,reg,value,I2Ccallback,width=8,bitoffset=0):
SPI=Find(self.D['I2C_devices'],'dev_name',dev)
@@ -36,7 +37,7 @@ class I2Cbitbang(I2Cdevices):
# data2=[regnr%256]+data2;
# regnr=int(regnr/256);
# data2=[Addr<<1,regnr]+data2;
# print(data2,Addr,Reg['reg_addr']);
# logging.info("%s %s %s",data2,Addr,Reg['reg_addr']);
if not(I2CbbTX(data2,I2Ccallback)): return False;
# return False;
data2=[(Addr<<1)+1];
@@ -49,14 +50,14 @@ class I2Cbitbang(I2Cdevices):
else: value[:]=data3[:];
if (width!=l1*8) or (bitoffset>0):
value[0]=UnMask(value[0],width,bitoffset)
#print("Received:",data3);
#logging.info("Received: %s",data3);
return True;
def I2CbbTX(data2,SetBit):
SetBit('SDIOdir',1) #Input, should be high
if SetBit('SDI',0,True)==0:
print("I2C line low!")
logging.error("I2C line low!")
return False;
#Start
SetBit('SDIOdir',0) #Output = low
@@ -64,18 +65,18 @@ def I2CbbTX(data2,SetBit):
for b in data2:
bit_array = "{0:{fill}8b}".format(b, fill='0')
#print(bit_array)
#logging.info(bit_array)
for bit in bit_array:
SetBit('SDIOdir',int(bit)) #input=high, output=low
SetBit('SCL',1)
SetBit('SCL',0)
SetBit('SDIOdir',1) #Input
#print(GetBit(SDI))
#logging.info(GetBit(SDI))
if SetBit('SDI',0,True)==1:
print("I2C: Not ACK")
logging.error("I2C: Not ACK")
return False;
SetBit('SCL',1)
#print(GetBit(SDI))
#logging.info(GetBit(SDI))
SetBit('SCL',0)
# SetBit(SDIOdir,0) #Output
@@ -88,7 +89,7 @@ def I2CbbTX(data2,SetBit):
def I2CbbRX(data1,data2,SetBit):
SetBit('SDIOdir',1) #Input, should be high
if SetBit('SDI',0,True)==0:
print("I2C ack: line low!")
logging.error("I2C ack: line low!")
return False;
#Start
SetBit('SDIOdir',0) #Output = low
@@ -97,18 +98,18 @@ def I2CbbRX(data1,data2,SetBit):
for b in data1:
bit_array = "{0:{fill}8b}".format(b, fill='0')
#print(bit_array)
#logging.info(bit_array)
for bit in bit_array:
SetBit('SDIOdir',int(bit)) #input=high, output=low
SetBit('SCL',1)
SetBit('SCL',0)
SetBit('SDIOdir',1) #Input
#print(GetBit(SDI))
#logging.info(GetBit(SDI))
if SetBit('SDI',0,True)==1:
print("I2C: Not ACK")
logging.error("I2C: Not ACK")
return False;
SetBit('SCL',1)
#print(GetBit(SDI))
#logging.info(GetBit(SDI))
SetBit('SCL',0)
for x in range(len(data2)):
Loading