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New apsct branch merge

Merged New apsct branch merge
new_apsct into master
Merged Paulus Kruger requested to merge new_apsct into master
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pypcc/config/APSCTTR.yaml
+ 134
− 59
@@ -9,17 +9,21 @@ drivers:
@@ -9,17 +9,21 @@ drivers:
type: i2c_dev #I2C devices
type: i2c_dev #I2C devices
parent: I2C
parent: I2C
status: APSCTTR_I2C_error
status: APSCTTR_I2C_error
- name: SPIbb1
- name: SPIbb1
type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
type: spibitbang3 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
parent: I2C_CLK
parent: I2C_CLK
devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
parameters: [4,7,5,6]
parameters: [4,7,5,6]
- name: SPIbb2
- name: SPIbb2
type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
type: spibitbang3 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
parent: I2C_CLK
parent: I2C_CLK
devreg: [IO2.GPIO1,IO2.GPIO1,IO2.GPIO1,IO2.GPIO1]
devreg: [IO2.GPIO1,IO2.GPIO1,IO2.GPIO1,IO2.GPIO1]
parameters: [4,7,5,6]
parameters: [4,7,5,6]
 
- name: LMP_GPIO
 
type: gpio_id
 
parameters: [21,20,16,12,7,8]
 
#This is the I2C devices in the RCU
#This is the I2C devices in the RCU
device_registers:
device_registers:
- name: IO
- name: IO
@@ -44,8 +48,12 @@ device_registers:
@@ -44,8 +48,12 @@ device_registers:
description: Input/Ouput port 2
description: Input/Ouput port 2
address: [1,3] #Read / Write address different
address: [1,3] #Read / Write address different
store: True
store: True
 
- name: POL1
 
address: 4
 
- name: POL2
 
address: 5
- name: PLL2
- name: PLL2 #200MHz on IO1
driver: SPIbb1
driver: SPIbb1
registers:
registers:
- name: PLL_stat
- name: PLL_stat
@@ -129,6 +137,14 @@ variables:
@@ -129,6 +137,14 @@ variables:
dtype: boolean
dtype: boolean
dim: 1
dim: 1
 
- name: LMP_ID
 
driver: LMP_GPIO
 
devreg: ROM.ID #this is ignored
 
width: 6
 
rw: ro
 
dtype: uint8
 
 
- name: APSCT_PCB_ID
- name: APSCT_PCB_ID
description: Unique PCB ID
description: Unique PCB ID
driver: I2C_CLK
driver: I2C_CLK
@@ -210,23 +226,52 @@ variables:
@@ -210,23 +226,52 @@ variables:
bitoffset: 3
bitoffset: 3
width: 1
width: 1
- name: APSCT_PLL_200MHz_locked_SPI
- name: APSCT_PLL_200MHz_lol
description: 0x81=locked
rw: ro
 
dtype: boolean
 
convert_unit: bool_invert
 
monitor: true
driver: I2C_CLK
driver: I2C_CLK
devreg: PLL2.PLL_stat
devreg: IO2.GPIO2
width: 8
bitoffset: 4
 
width: 1
 
 
- name: APSCT_PLL_160MHz_lol
rw: ro
rw: ro
dtype: uint8
dtype: boolean
debug: True
convert_unit: bool_invert
 
monitor: true
 
driver: I2C_CLK
 
devreg: IO2.GPIO2
 
bitoffset: 5
 
width: 1
- name: APSCT_PLL_160MHz_locked_SPI
- name: APSCT_PLL_clr_lol
description: 0x81=locked
rw: rw
 
dtype: boolean
 
# monitor: true
driver: I2C_CLK
driver: I2C_CLK
devreg: PLL1.PLL_stat
devreg: IO1.GPIO2
width: 8
bitoffset: 4
rw: ro
width: 1
dtype: uint8
debug: True
# - name: APSCT_PLL_200MHz_locked_SPI
 
# description: 0x81=locked
 
# driver: I2C_CLK
 
# devreg: PLL2.PLL_stat
 
# width: 8
 
# rw: ro
 
# dtype: uint8
 
# debug: True
 
 
# - name: APSCT_PLL_160MHz_locked_SPI
 
# description: 0x81=locked
 
# driver: I2C_CLK
 
# devreg: PLL1.PLL_stat
 
# width: 8
 
# rw: ro
 
# dtype: uint8
 
# debug: True
# - name: [APSCT_PLL_r3,APSCT_PLL_r5,APSCT_PLL_r6]
# - name: [APSCT_PLL_r3,APSCT_PLL_r5,APSCT_PLL_r6]
# driver: I2C_CLK
# driver: I2C_CLK
@@ -297,6 +342,7 @@ methods:
@@ -297,6 +342,7 @@ methods:
- APSCT_PCB_version : Update
- APSCT_PCB_version : Update
- APSCT_PCB_number : Update
- APSCT_PCB_number : Update
- APSCT_PWR_on: Update
- APSCT_PWR_on: Update
 
- LMP_ID: Update
- APSCT_PWR_PLL_200MHz_on: Update
- APSCT_PWR_PLL_200MHz_on: Update
- APSCT_PLL_200MHz_locked: Update
- APSCT_PLL_200MHz_locked: Update
- APSCT_PLL_200MHz_error: Update
- APSCT_PLL_200MHz_error: Update
@@ -304,24 +350,41 @@ methods:
@@ -304,24 +350,41 @@ methods:
- APSCT_PLL_160MHz_locked: Update
- APSCT_PLL_160MHz_locked: Update
- APSCT_PLL_160MHz_error: Update
- APSCT_PLL_160MHz_error: Update
- APSCT_PPS_ignore : Update
- APSCT_PPS_ignore : Update
 
- APSCT_PLL_clr_lol: Update
 
- APSCT_PLL_200MHz_lol: Update
 
- APSCT_PLL_160MHz_lol: Update
 
# - name: APSCT_clr_lol
 
# driver: I2C_CLK
 
# description: Clear lock-off-lock
 
# instructions:
 
# - APSCTTR_I2C_error : 0
 
- name: APSCT_200MHz_on
- name: APSCT_200MHz_on
driver: I2C_CLK
driver: I2C_CLK
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
instructions:
instructions:
- APSCTTR_I2C_error : 0
- APSCTTR_I2C_error : 0
 
- IO1.POL1: 0
 
- IO1.POL2: 0
 
- IO2.POL1: 0
 
- IO2.POL2: 0
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF2: 0x00
- IO1.CONF2: 0x00
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO2.CONF2: 0x03 #
- IO2.CONF2: 0xFF #
- IO1.GPIO1: 0x42 #0100 0010 high:200MHz PLL enable, CS high
- IO1.GPIO1: 0x42 #0100 0010 high:200MHz PLL enable, CS high
- IO1.GPIO2: 0xF8 #PWR enable ##Check if not 4??
# - IO1.GPIO2: 0xF8 #PWR enable ##Check if not 4??
 
- IO1.GPIO2: 0x28 #PWR enable
- IO2.GPIO1: 0x00 #All low
- IO2.GPIO1: 0x00 #All low
- IO2.GPIO2: 0x00 #All low (just inputs)
# - IO2.GPIO2: 0x00 #All low (just inputs)
- WAIT: 200
- WAIT: 200
- APSCT_PLL200_setup: 0
- APSCT_PLL200_setup: 0
- WAIT: 200 #ms to wait before checking lock
- WAIT: 200 #ms to wait before checking lock
 
- APSCT_PLL_clr_lol: 1
 
- WAIT: 10 #ms
 
- APSCT_PLL_clr_lol: 0
- APSCTTR_Update: 0 #refresh all settings
- APSCTTR_Update: 0 #refresh all settings
- name: APSCT_160MHz_on
- name: APSCT_160MHz_on
@@ -329,18 +392,25 @@ methods:
@@ -329,18 +392,25 @@ methods:
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
instructions:
instructions:
- APSCTTR_I2C_error : 0
- APSCTTR_I2C_error : 0
 
- IO1.POL1: 0
 
- IO1.POL2: 0
 
- IO2.POL1: 0
 
- IO2.POL2: 0
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF2: 0x00
- IO1.CONF2: 0x00
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO2.CONF2: 0x03 #
- IO2.CONF2: 0xFF #
- IO1.GPIO1: 0x00
- IO1.GPIO1: 0x00
- IO1.GPIO2: 0x08 #PWR enable ##Check if not 4??
- IO1.GPIO2: 0x08 #PWR enable ##Check if not 4??
- IO2.GPIO1: 0x42 #0100 0010 high:160MHz PLL enable, CS high
- IO2.GPIO1: 0x42 #0100 0010 high:160MHz PLL enable, CS high
- IO2.GPIO2: 0x00 #All low (just inputs)
# - IO2.GPIO2: 0x00 #All low (just inputs)
- WAIT: 200
- WAIT: 200
- APSCT_PLL160_setup: 0
- APSCT_PLL160_setup: 0
- WAIT: 200 #ms to wait before checking lock
- WAIT: 200 #ms to wait before checking lock
 
- APSCT_PLL_clr_lol: 1
 
- WAIT: 10 #ms
 
- APSCT_PLL_clr_lol: 0
- APSCTTR_Update: 0 #refresh all settings
- APSCTTR_Update: 0 #refresh all settings
- name: APSCT_off
- name: APSCT_off
@@ -358,45 +428,50 @@ methods:
@@ -358,45 +428,50 @@ methods:
driver: I2C_CLK
driver: I2C_CLK
debug: true
debug: true
instructions:
instructions:
# - PLL2.0x03: 0x08 #Set power, this is default
- PLL2.0x04: 0x01 #div a
- PLL2.0x04: 0xCF #
- PLL2.0x05: 0x00 #div b, high
- PLL2.0x05: 0x97 #was 97, set lock time = =x17?
- PLL2.0x06: 0x14 #dib b, low
- PLL2.0x06: 0x10
- PLL2.0x07: 0x00 # No LOR
- PLL2.0x08: 0x3B # Charge pump normal + Status bit
- PLL2.0x07: 0x04 #Stop R divider
- PLL2.0x09: 0x30 # Charge pump current
- PLL2.0x08: 0x01 #Set R divider
- PLL2.0x0A: 0x00 # Fixed Divide 1
- PLL2.0x07: 0x00 #Start R divider
- PLL2.0x0B: 0x00
- PLL2.0x0C: 0x01
- PLL2.0x09: 0x10 #Stop N divider
- PLL2.0x45: 0x00 # CLK2 as feedback clock input
- PLL2.0x0A: 0x14 #Set N divider=20, 200MHz/20=10MHz = input clock
- PLL2.0x3d: 0x08 # OUT0 ON LVDS Standard
- PLL2.0x09: 0x00 #Start N divider
- PLL2.0x3e: 0x0a # OUT1 OFF
- PLL2.0x3f: 0x0a # OUT2 OFF
- PLL2.0x0D: 0x01 #Divider output 1=1
- PLL2.0x40: 0x03 # OUT3 OFF
- PLL2.0x0F: 0x01 #Divider output 2=1
- PLL2.0x41: 0x02 # OUT4 ON LVDS Standard
- PLL2.0x11: 0x01 #Divider output 3=1
- PLL2.0x4b: 0x80 # OUT0 bypass divider
- PLL2.0x13: 0x01 #Divider output 4=1
- PLL2.0x4d: 0x80 # OUT1 bypass divider
 
- PLL2.0x4f: 0x80 # OUT2 bypass divider
 
- PLL2.0x51: 0x80 # OUT3 bypass divider
 
- PLL2.0x53: 0x80 # OUT4 bypass divider
 
- PLL2.0x5a: 0x0f # Update registers
- name: APSCT_PLL160_setup
- name: APSCT_PLL160_setup
driver: I2C_CLK
driver: I2C_CLK
debug: true
debug: true
instructions:
instructions:
# - PLL1.0x03: 0x08 #Set power, this is default
- PLL1.0x04: 0x01 #div a
- PLL1.0x04: 0xCF #
- PLL1.0x05: 0x00 #div b, high
- PLL1.0x05: 0x97 #was 97, set lock time = =x17?
- PLL1.0x06: 0x10 #dib b, low
- PLL1.0x06: 0x10
- PLL1.0x07: 0x00 # No LOR
- PLL1.0x08: 0x3B # Charge pump normal + Status bit
- PLL1.0x07: 0x04 #Stop R divider
- PLL1.0x09: 0x30 # Charge pump current
- PLL1.0x08: 0x01 #Set R divider
- PLL1.0x0A: 0x00 # Fixed Divide 1
- PLL1.0x07: 0x00 #Start R divider
- PLL1.0x0B: 0x00
- PLL1.0x0C: 0x01
- PLL1.0x09: 0x10 #Stop N divider
- PLL1.0x45: 0x00 # CLK2 as feedback clock input
- PLL1.0x0A: 0x10 #Set N divider=16, 160MHz/16=10MHz = input clock
- PLL1.0x3d: 0x08 # OUT0 ON LVDS Standard
- PLL1.0x09: 0x00 #Start N divider
- PLL1.0x3e: 0x0a # OUT1 OFF
- PLL1.0x3f: 0x0a # OUT2 OFF
- PLL1.0x0D: 0x01 #Divider output 1=1
- PLL1.0x40: 0x03 # OUT3 OFF
- PLL1.0x0F: 0x01 #Divider output 2=1
- PLL1.0x41: 0x02 # OUT4 ON LVDS Standard
- PLL1.0x11: 0x01 #Divider output 3=1
- PLL1.0x4b: 0x80 # OUT0 bypass divider
- PLL1.0x13: 0x01 #Divider output 4=1
- PLL1.0x4d: 0x80 # OUT1 bypass divider
- PLL1.0x4f: 0x80 # OUT2 bypass divider
- PLL1.0x51: 0x80 # OUT3 bypass divider
- PLL1.0x53: 0x80 # OUT4 bypass divider
 
- PLL1.0x5a: 0x0f # Update registers