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Commit e5d9423c authored by Paulus Kruger's avatar Paulus Kruger
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UNB2 YAML first draft

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config/UNB2.yaml
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version: "0.0" version: "0.0"
description: "UNB2 LTS" description: "UNB2 DTS first draft"
drivers: drivers:
- name: I2C1 - name: I2C1
type: UNB2_switch #Special driver mapping internal i2c line address to the 3 switches. type: UNB2_switch
#Address -> switch states -> array of i2c-devices
#00:2F -> [0:1][0:3][0:3,6:7] -> QSFP
#30:38 -> [0:1][0:3][4] -> DDR4
#40:48 -> [0:1][0:3][5] -> FPGA_PS
#80:81 -> [0:1][4] -> PS
#A0:A1 -> [0:1][5] -> Front panel
devreg: [APSCT_SWITCH.MASK,UB2_SWITCH1.MASK,UB2_SWITCH2.MASK] devreg: [APSCT_SWITCH.MASK,UB2_SWITCH1.MASK,UB2_SWITCH2.MASK]
parameters: [1,0,0,0] #I2C port number, 3x switch reset pins parameters: [1,0,0,0] #I2C port number, 3x switch reset pins
- name: switch_UNB2
- name: d_QSFP type: i2c_array
type: i2c_array #An array of similar devices connected to an I2C switch
parent: I2C1 parent: I2C1
parameters: [0,48] #start,number of QSFP (2 UB x 2 nodes * 6 QSFP) parameters: [0,1]
- name: d_DDR4 - name: switch_PS
type: i2c_array type: i2c_array
parent: I2C1 parent: I2C1
parameters: [0x30,8] parameters: [0,1, 4]
- name: d_FPGA_PS - name: switch_FP
type: i2c_array type: i2c_array
parent: I2C1 parent: I2C1
parameters: [0x40,48] parameters: [0,1, 5]
- name: d_PS - name: switch_QSFP
type: i2c_array #An array of similar devices connected to an I2C switch
parent: I2C1
parameters: [0,1, 0,3, 0,3, 6,7] #Parameters: APSCT_Switch, main switch, 2nd switch, 2nd switch
- name: switch_DDR4
type: i2c_array type: i2c_array
parent: I2C1 parent: I2C1
parameters: [0x80,2] parameters: [0,1, 0,3, 4,4]
- name: d_front_panel - name: switch_FPGA_PS
type: i2c_array type: i2c_array
parent: I2C1 parent: I2C1
parameters: [0xA0,2] parameters: [0,1, 0,3, 5,5]
# - name: GPIO - name: GPIO
# type: GPIO type: GPIO
# parameters: [1] #pin numbers
#This is the I2C devices in the RCU #This is the I2C devices in the RCU
...@@ -76,44 +72,192 @@ device_registers: ...@@ -76,44 +72,192 @@ device_registers:
address: [0,1] #Read / Write address different address: [0,1] #Read / Write address different
store: True store: True
- name: POL_FPGA_CORE
address: 0x01
driver: d_FPGA_PS
device: BMR4xx
registers:
- name: READ_VOUT
address: 0x8B
- name: READ_IOUT
address: 0x8C
- name: READ_TEMP
address: 0x8D
variables: variables:
#When I2C bus timeout, bus_OK set to False. Can we set to True again to retry.
- name: UNB2_I2C_bus_OK
driver: switch_UNB2
rw: variable
dtype: boolean
dim: 2
- name: UNB2_I2C_bus_QSFP_OK
driver: switch_QSFP
rw: variable
dtype: boolean
dim: 48
- name: UNB2_I2C_bus_DDR4_OK
driver: switch_QSFP
rw: variable
dtype: boolean
dim: 8
- name: UNB2_I2C_bus_FPGA_PS_OK
driver: switch_FPGA_PS
rw: variable
dtype: boolean
dim: 8
- name: UNB2_I2C_bus_PS_OK
driver: switch_PS
rw: variable
dtype: boolean
dim: 2
##Central MP for whole Uniboard2
- name: UNB2_mask - name: UNB2_mask
rw: variable #translator variable rw: variable #translator variable
dtype: boolean dtype: boolean
dim: 2 dim: 2
- name: UNB2_Power_ON_OFF
driver: GPIO
mask: UNB2_mask
width: 1
rw: rw
dtype: boolean
dim: 2
- name: UNB2_Front_Panel_LED - name: UNB2_Front_Panel_LED
description: LED on front panel description: bit 0=Red, 1=Blue, 2=Green
mask: UNB2_mask mask: UNB2_mask
driver: switch_FP
devreg: FP_IO.GPIO devreg: FP_IO.GPIO
driver: d_front_panel
rw: rw
dtype: uint8
bitoffset: 4 bitoffset: 4
width: 3 width: 3
rw: rw
dtype: uint8
dim: 2
- name: UNB2_EEPROM_Serial_Number
driver: switch_UNB2
devreg: 0x50.0
width: 80 #10 characters
rw: ro
dtype: string
dim: 2
- name: UNB2_EEPROM_ID
driver: switch_UNB2
mask: UNB2_I2C_bus_OK
devreg: 0x50.0xFC
width: 32
rw: ro
dtype: uint32
dim: 2
- name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT,UNB2_DC_DC_48V_12V_IOUT,UNB2_DC_DC_48V_12V_TEMP]
driver: switch_PS
mask: UNB2_I2C_bus_PS_OK
devreg: [0x2C.0x88,0x2C.0x8B,0x2C.0x8C,0x2C.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 2
- name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_VOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_QSFP_N23_TEMP]
driver: switch_PS
mask: UNB2_I2C_bus_PS_OK
devreg: [0x2.0x8B,0x2.0x8C,0x2.0x8D,0x1.0x8B,0x1.0x8C,0x1.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 2 dim: 2
- name: UNB2_POL_FPGA_CORE_VOUT - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_SWITCH_PHY_TEMP]
driver: d_FPGA_PS driver: switch_PS
devreg: POL_FPGA_CORE.READ_VOUT mask: UNB2_I2C_bus_PS_OK
devreg: [0xF.0x8B,0xF.0x8C,0xF.0x8D,0xE.0x8B,0xE.0x8C,0xE.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 2
- name: [UNB2_POL_CLOCK_VOUT,UNB2_POL_CLOCK_IOUT,UNB2_POL_CLOCK_TEMP]
driver: switch_PS
mask: UNB2_I2C_bus_PS_OK
devreg: [0xD.0x8B,0xD.0x8C,0xD.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 2
##Local MP per FPGA node
- name: UNB2_FPGA_DDR4_SLOT_TEMP
description: Signed I2C!
driver: switch_DDR4
mask: UNB2_I2C_bus_DDR4_OK
devreg: [0x18.0x5,0x19.0x5]
width: 13
rw: ro
dtype: double
scale: 0.0625
dim: 16
- name: UNB2_FPGA_DDR4_SLOT0_PART_NUMBER
driver: switch_DDR4
mask: UNB2_I2C_bus_DDR4_OK
devreg: [0x18.0x149,0x19.0x149]
width: 160
rw: ro
dtype: string
dim: 16
- name: [UNB2_POL_FPGA_CORE_VOUT,UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_ERAM_TEMP]
driver: switch_FPGA_PS
mask: UNB2_I2C_bus_FGPA_PS_OK
devreg: [0x1.0x8B,0x1.0x8C,0x1.0x8D,0xD.0x8B,0xD.0x8C,0xD.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 8
- name: [UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_TXGXB_IOUT,PUNB2_OL_FPGA_TXGXB_TEMP]
driver: switch_FPGA_PS
mask: UNB2_I2C_bus_FGPA_PS_OK
devreg: [0xE.0x8B,0xE.0x8C,0xE.0x8D,0xF.0x8B,0xF.0x8C,0xF.0x8D]
width: 16
rw: ro
dtype: double
scale: 1.2207e-4 #2^-13
dim: 8
- name: [UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_VOUT,UNB2_FPGA_POL_PGM_IOUT,UNB2_FPGA_POL_PGM_TEMP]
driver: switch_FPGA_PS
mask: UNB2_I2C_bus_FGPA_PS_OK
devreg: [0x10.0x8B,0x10.0x8C,0x10.0x8D,0x11.0x8B,0x11.0x8C,0x11.0x8D]
width: 16 width: 16
rw: ro rw: ro
dtype: double dtype: double
scale: 1.2207e-4 #2^-13 scale: 1.2207e-4 #2^-13
dim: 8 dim: 8
mask: UNB2_node_mask
##Local MP per FPGA node, QSFP cage
- name: UNB2_FPGA_QSFP_CAGE_TEMP
description: Signed I2C!
driver: switch_QSFP
mask: UNB2_I2C_bus_QSFP_OK
devreg: 0x50.0x16
width: 16
rw: ro
dtype: double
scale: 0.0625 #TBC
dim: 48
- name: UNB2_FPGA_QSFP_CAGE_LOS
description: Bits for 4 TX, 4 RX channels
driver: switch_QSFP
mask: UNB2_I2C_bus_QSFP_OK
devreg: 0x50.0x03
width: 8
rw: ro
dtype: uint8
dim: 48
methods: methods:
- name: UNB2_on - name: UNB2_on
......
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