Merge branch 'fix-unb2-dim2s' into 'master'

Swap UNB2 dimensions around to represent 2 sets of everything.

See merge request !15

config/UNB2TR.yaml

@@ -105,19 +105,19 @@ variables:
      rw:  ro
      dtype: uint8
      dim: 48
-     dim2: [2,24]
+     dim2: [24,2]
    - name: UNB2TR_I2C_bus_DDR4_error
      driver: switch_QSFP
      rw:  ro
      dtype: uint8
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
    - name: UNB2TR_I2C_bus_FPGA_PS_error
      driver: switch_FPGA_PS
      rw:  ro
      dtype: uint8
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
    - name: UNB2TR_I2C_bus_PS_error
      driver: switch_PS
      rw:  ro
@@ -258,7 +258,7 @@ variables:
      dtype: double
      scale: 0.0625 
      dim: 16
-     dim2: [2,8]
+     dim2: [8,2]
      monitor: true
 
    - name: UNB2_FPGA_DDR4_SLOT_PART_NUMBER
@@ -268,7 +268,7 @@ variables:
      rw:  hidden #ro
      dtype: string
      dim: 16
-     dim2: [2,8]
+     dim2: [8,2]
 #     monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
@@ -279,7 +279,7 @@ variables:
      dtype: double
      scale: smbus_2bytes_to_float
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
      monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
@@ -290,7 +290,7 @@ variables:
      dtype: double
      scale: smbus_2bytes_to_float
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
      monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_VOUT]
@@ -302,7 +302,7 @@ variables:
      endian: "<"
      scale: 1.220703125e-4 #2^-13
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
      monitor: true
 
    - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
@@ -314,7 +314,7 @@ variables:
      endian: "<"
      scale: 2.44140625e-4 #2^-12
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
      monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
@@ -324,7 +324,7 @@ variables:
      rw:  ro
      dtype: uint8
      dim: 8
-     dim2: [2,4]
+     dim2: [4,2]
      debug: true
      monitor: true
 
@@ -339,7 +339,7 @@ variables:
      scale: 3.90625e-3 #1/256
      convert_unit: temp_check
      dim: 48
-     dim2: [2,24]
+     dim2: [24,2]
      monitor: true
 
    - name: UNB2_FPGA_QSFP_CAGE_LOS
@@ -350,7 +350,7 @@ variables:
      rw:  ro
      dtype: uint8
      dim: 48
-     dim2: [2,24]
+     dim2: [24,2]
      monitor: true
 
 methods: