DTS-lab-lite, conf changed, PCC object removed

VarTable.py

 import yamlconfig as yc
-
+import sys
 RW={'ro':'_R','rw':'_R/_RW','variable':'_RW'}
 
-Y=yc.yamlconfig('RECVTR')
+Y=yc.yamlconfig(sys.argv[1])
 sep='\t'
 #Sort alphabetically
 names=[(v['name']).upper() for v in Y.getvars()]
@@ -12,8 +12,9 @@ for i0 in SI:
     v=Y.getvar1(i0)
 #for v in Y.getvars():
     if v.get("debug",False): continue;
+    if v.get("rw",False)=='hidden': continue;
     S=v['name']+sep
-    S+=str(v['dim'])+sep
+    S+=str(v.get('dim',1))+sep
     S+=str(v['dtype'])+sep
     S+=RW[v['rw']]+sep
     S+=v.get('mask','')+sep

config/APSCTTR.yaml

+version: "1.0"
+description: "1234"
+
+drivers:
+ - name: I2C
+   type: i2c
+   parameters: [5] #I2C port number
+ - name: I2C_CLK
+   type: i2c_dev #I2C devices
+   parent: I2C
+   status: CLK_I2C_error
+ - name: SPIbb1 
+   type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+   parent: I2C_CLK
+   devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
+   parameters: [4,7,5,6]
+
+#This is the I2C devices in the RCU
+device_registers:
+ - name: IO1
+   description: IO-Expander
+   address: 0x20
+   driver: I2C_CLK
+   registers:
+   - name: CONF1
+     description: Direction of port1
+     address: 6
+     store: True
+   - name: GPIO1
+     description: Input/Ouput port 1
+     address: [0,2]  #Read / Write address different
+     store: True
+
+ - name: PLL
+   driver: SPIbb1
+   registers:
+    - name: PLL_stat
+      description: PLL locked status
+      address: 0x0
+    - {name: r3, address: 0x03}
+    - {name: r5, address: 0x05}
+    - {name: r6, address: 0x06}
+
+ - name: ROM
+   address: 0x50
+   driver: I2C_PU
+   registers:
+   - name: ID
+     description: Random
+     address: 0xfc
+   - name: Version
+     description: Set in production
+     address: 0
+
+
+variables:
+  - name: APSCT_I2C_error
+    description: When >0 indicates an I2C error
+    driver: I2C_CLK
+    rw:  ro #server RW variable, not linked to IO
+    dtype: uint8
+
+  - name: APSCTTR_translator_busy
+    description: False when idle
+    rw:  ro #server variable, not linked to IO
+    dtype: boolean
+    dim: 1
+
+  - name: APSCT_ID
+    description: Unique PCB ID
+    driver: I2C_CLK
+    devreg:  ROM.ID
+    width: 32
+    rw:  ro
+    dtype: uint32
+
+  - name: APSCT_version
+    description: Version number
+    driver: I2C_CLK
+    devreg:  ROM.Version
+    width: 80  #10 characters
+    rw:  ro
+    dtype: string
+
+
+  - name: CLK_PWR_on
+    description: CLK power status. True=ON. Controlled by CLK_ON and CLK_OFF
+    rw:  ro
+    dtype: boolean
+    driver: I2C_CLK
+    devreg:  IO1.GPIO1
+    bitoffset: 1
+    width: 1
+
+
+  - name: CLK_PLL_locked
+    description: First status pin give lock status
+    rw:  ro
+    dtype: boolean
+    monitor: true
+    driver: I2C_CLK
+    devreg:  IO1.GPIO1
+    bitoffset: 2
+    width: 1
+
+  - name: CLK_PLL_error
+    description: Second status pin give error
+    rw:  ro
+    dtype: boolean
+    monitor: true
+    driver: I2C_CLK
+    devreg:  IO1.GPIO1
+    bitoffset: 3
+    width: 1
+
+  - name: CLK_PLL_locked_SPI
+    description: 0x81=locked
+    driver: I2C_CLK
+    devreg:  PLL.PLL_stat
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+  - name: [CLK_PLL_r3,CLK_PLL_r5,CLK_PLL_r6]
+    driver: I2C_CLK
+    devreg:  [PLL.r3,PLL.r5,PLL.r6]
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+  - name: RCU_IO1_GPIO1
+    driver: I2C_CLK
+    devreg:  IO1.GPIO1
+    width: 8
+    rw:  ro
+    dtype: uint8
+    mask: RCU_mask
+    debug: True
+
+methods:
+  - name: APSCTTR_Init #Called after startup to load. Should have all stored registers  
+    driver: I2C_CLK
+    debug: True
+    instructions:   
+      - APSCT_I2C_error : 0
+      - RCU_IO1_GPIO1 : Update
+      - IO1.CONF1: Update
+      - CLK_PWR_on: Update
+      - CLK_PLL_locked: Update
+      - CLK_PLL_error: Update
+      - APSCT_ID : Update
+      - APSCT_version : Update
+
+
+  - name: CLK_on  
+    driver: I2C_CLK
+    description: Configure clock. Monitored using CLK_PWR_on, CLK_PLL_error and CLK_PLL_locked
+    instructions:   
+     - APSCT_I2C_error : 0
+     - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO1.GPIO1: 0x42 #0100 0010 high:PWR enable, CS
+     - CLK_PWR_on: Update
+     - WAIT: 200         #ms to wait before checking lock
+     - CLK_PLL_setup: 0
+     - WAIT: 100         #ms to wait before checking lock
+     - CLK_PLL_locked: Update
+
+  - name: CLK_off  
+    driver: I2C_CLK
+    description: Switch clock off. Monitored using CLK_PWR_on
+    instructions:   
+     - APSCT_I2C_error : 0
+     - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO1.GPIO1: 0x00 #all low
+     - CLK_PWR_on: Update
+     - CLK_PLL_locked: Update
+
+  - name: CLK_PLL_setup  
+    driver: I2C_CLK
+    debug: true
+    instructions:   
+#   - PLL.0x03: 0x08 #Set power, this is default
+    - PLL.0x05: 0x17 #was 97, set lock time
+    - PLL.0x06: 0x10
+
+    - PLL.0x07: 0x04 #Stop R divider
+    - PLL.0x08: 0x01 #Set R divider
+    - PLL.0x07: 0x00 #Start R divider
+
+    - PLL.0x09: 0x10 #Stop N divider
+    - PLL.0x0A: 0x14 #Set N divider=20, 200MHz/20=10MHz = input clock
+    - PLL.0x09: 0x00 #Start N divider
+
+    - PLL.0x0D: 0x01 #Divider output 1=1 
+    - PLL.0x0F: 0x01 #Divider output 2=1
+    - PLL.0x11: 0x01 #Divider output 3=1
+    - PLL.0x13: 0x01 #Divider output 4=1
+
+ 

config/APSPUTR.yaml

+1version: "1.0"
+description: "1234"
+
+drivers:
+ - name: I2C
+   type: i2c_smbus
+   parameters: [4] #I2C port number
+ - name: I2C_PU
+   type: i2c_dev #I2C devices
+   parent: I2C
+   status: APSPU_I2C_error
+
+#This is the I2C devices in the RCU
+device_registers:
+ - name: ROM
+   address: 0x50
+   driver: I2C_PU
+   registers:
+   - name: ID
+     description: Random
+     address: 0xfc
+   - name: Version
+     description: Set in production
+     address: 0
+ 
+
+ - name: MAX
+   description: MAX6620 fan speed controller
+   address: 0x29
+   driver: I2C_PU
+   registers:
+   - name: GLOBAL
+     address: 0x00
+   - name: TACH1
+     address: 0x10
+   - name: TACH2
+     address: 0x12
+   - name: TACH3
+     address: 0x14
+
+
+variables:
+  - name: APSPU_I2C_error
+    driver: I2C_PU
+    rw:  ro #server RW variable, not linked to IO
+    dtype: uint8
+
+  - name: APSPUTR_translator_busy
+    description: False when idle
+    rw:  ro #server variable, not linked to IO
+    dtype: boolean
+
+  - name: APSPU_ID
+    description: Unique PCB ID
+    driver: I2C_PU
+    devreg:  ROM.ID
+    width: 32
+    rw:  ro
+    dtype: uint32
+
+  - name: APSPU_version
+    description: Version number
+    driver: I2C_PU
+    devreg:  ROM.Version
+    width: 80  #10 characters
+    rw:  ro
+    dtype: string
+
+
+  - name: [APSPU_LBA_VOUT,APSPU_RCU2A_VOUT,APSPU_RCU2D_VOUT]
+    driver: I2C_PU
+    devreg:  [0x3C.0x8B,0x3D.0x8B,0x3E.0x8B]
+    width: 16
+    rw:  ro
+    dtype: double
+    endian: "<"
+    scale: 4.8828e-4 #2^-11
+    monitor: true
+
+  - name: [APSPU_LBA_IOUT,APSPU_RCU2A_IOUT,APSPU_RCU2D_IOUT]
+    driver: I2C_PU
+    devreg:  [0x3C.0x8C,0x3D.0x8C,0x3E.0x8C]
+    width: 16
+    rw:  ro
+    dtype: double
+    scale: smbus_2bytes_to_float
+    monitor: true
+
+  - name: [APSPU_LBA_TEMP,APSPU_RCU2A_TEMP,APSPU_RCU2D_TEMP]
+    driver: I2C_PU
+    devreg:  [0x3C.0x8D,0x3D.0x8D,0x3E.0x8D]
+    width: 16
+    rw:  ro
+    dtype: double
+    scale: smbus_2bytes_to_float
+    monitor: true
+
+  - name: [APSPU_FAN_period1,APSPU_FAN_period2,APSPU_FAN_period3]
+    driver: I2C_PU
+    devreg:  [MAX.TACH1,MAX.TACH2,MAX.TACH3]
+    bitoffset: 5
+    width: 11
+    rw:  ro
+    dtype: double
+    scale: 1.52588e-5 #FAN_TACHS/TACH_COUNT_FREQ/TACH_PERIODS = 1/8192/16 *2
+#    monitor: true
+
+methods:
+  - name: APSPUTR_Init #Called after startup to load. Should have all stored registers  
+    driver: I2C_PU
+    debug: True
+    instructions:   
+      - APSPU_ID : Update
+      - APSPU_version : Update
+
+  - name: APSPU_FanOn
+    driver: I2C_PU
+    instructions:   
+      - MAX.GLOBAL : 0x02; #Run monitor
+      - MAX.0x02 : 0x88;
+      - MAX.0x06 : 0x80; # int((math.log(TACH_PERIODS{16}) / math.log(2))) << 5, 
+      - MAX.0x03 : 0x88;
+      - MAX.0x07 : 0x80;
+      - MAX.0x04 : 0x88;
+      - MAX.0x08 : 0x80;

config/UNB2TR.yaml

+version: "0.0"
+description: "UNB2 DTS first draft" 
+
+drivers:
+ - name: I2C1
+   type: i2c_switch2 
+   devreg: [APSCT_SWITCH.MASK,UB2_SWITCH1.MASK,UB2_SWITCH2.MASK] 
+   parameters: [3,0,0,0] #I2C port number, 3x switch reset pins 
+
+ - name: switch_UNB2
+   type: i2c_array
+   parent: I2C1
+   parameters: [0,1,10] 
+   status: UNB2_I2C_bus_error
+
+ - name: switch_PS
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  4,4] 
+   status: UNB2_I2C_bus_PS_error
+
+ - name: switch_FP
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  5,5] 
+   status: UNB2_I2C_bus_FP_error
+
+ - name: switch_QSFP 
+   type: i2c_array2 #An array of similar devices connected to an I2C switch
+   parent: I2C1
+   parameters: [0,1,  0,3,  0,3, 6,7] #Parameters: APSCT_Switch, main switch, 2nd switch, 2nd switch
+   status: UNB2_I2C_bus_QSFP_error
+
+ - name: switch_DDR4
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  0,3,  4,4]
+   status: UNB2_I2C_bus_DDR4_error
+
+ - name: switch_FPGA_PS
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  0,3,  5,5] 
+   status: UNB2_I2C_bus_FPGA_PS_error
+
+ - name: GPIO
+   type: gpio
+
+  
+#This is the I2C devices in the RCU
+device_registers:
+- name: APSCT_SWITCH #not in LTS
+  description: Uniboard select switch on APSCT
+  address: 0x70
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+- name: UB2_SWITCH1
+  description: UNB2 primary switch
+  address: 0x71
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+- name: UB2_SWITCH2
+  description: UNB2 secondary switch
+  address: 0x72
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+
+- name: FP_IO
+  description: IO-Expander for front panel
+  address: 0x41
+  device: PCA9536
+  driver: d_front_panel
+  registers:
+  - name: CONF #default 0xff = all input
+    description: Direction of GPIO
+    address: 3
+  - name: GPIO
+    description: Input/Ouput port 
+    address: [0,1]  #Read / Write address different
+    store: True
+
+
+variables:
+
+#When I2C bus timeout, bus_error set to False.  Can we set to True again to retry.
+   - name: UNB2_I2C_bus_error
+     driver: switch_UNB2
+     rw:  ro
+     dtype: uint8
+     dim: 2
+   - name: UNB2_I2C_bus_FP_error
+     driver: switch_UNB2
+     rw:  hidden
+     dtype: uint8
+     dim: 2
+   - name: UNB2_I2C_bus_QSFP_error
+     driver: switch_QSFP
+     rw:  ro
+     dtype: uint8
+     dim: 48
+   - name: UNB2_I2C_bus_DDR4_error
+     driver: switch_QSFP
+     rw:  ro
+     dtype: uint8
+     dim: 8
+   - name: UNB2_I2C_bus_FPGA_PS_error
+     driver: switch_FPGA_PS
+     rw:  ro
+     dtype: uint8
+     dim: 8
+   - name: UNB2_I2C_bus_PS_error
+     driver: switch_PS
+     rw:  ro
+     dtype: uint8
+     dim: 2
+
+   - name: UNB2TR_translator_busy
+     description: False when idle
+     rw:  ro #server variable, not linked to IO
+     dtype: boolean
+     dim: 1
+
+##Central MP for whole Uniboard2
+   - name: UNB2_mask
+     rw:  variable #translator variable
+     dtype: boolean
+     dim: 2
+
+   - name: UNB2_Power_ON_OFF
+     driver: GPIO
+     mask: UNB2_mask
+     width: 1
+     rw:  hidden #ro
+     dtype: boolean
+     dim: 2
+
+   - name: UNB2_Front_Panel_LED
+     description: bit 0=Red, 1=Blue, 2=Green
+     mask: UNB2_mask
+     driver: switch_FP
+     devreg: FP_IO.GPIO
+     bitoffset: 4
+     width: 3
+     rw:  rw
+     dtype: uint8
+     dim: 2
+
+   - name: UNB2_EEPROM_Serial_Number
+     driver: switch_UNB2
+     devreg: 0x50.0
+     width: 80  #10 characters
+     rw:  ro
+     dtype: string
+     dim: 2
+
+   - name: UNB2_EEPROM_Unique_ID
+     driver: switch_UNB2
+     devreg: 0x50.0xFC
+     width: 32
+     rw:  ro
+     dtype: uint32
+     dim: 2
+
+
+   - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT]
+     driver: switch_PS
+     devreg:  [0x2C.0x88,0x2C.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 4.8828125e-4 #2^-11
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_VOUT_MODE,UNB2_POL_QSFP_N01_VOUT_MODE,UNB2_POL_QSFP_N23_VOUT_MODE,UNB2_POL_SWITCH_1V2_VOUT_MODE,UNB2_POL_SWITCH_PHY_VOUT_MODE,UNB2_POL_CLOCK_VOUT_MODE]
+     driver: switch_PS
+     devreg:  [0x2C.0x20,0x2.0x20,0x1.0x20,0xF.0x20,0xE.0x20,0xD.0x20]
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 2
+     debug: true
+     monitor: true
+
+   - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
+     driver: switch_PS
+     devreg:  [0x2.0x8B,0x1.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 1.220703125e-4 #2^-13
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
+     driver: switch_PS
+     devreg:  [0xF.0x8B,0xE.0x8B,0xD.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 2.44140625e-4 #2^-12
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+     driver: switch_PS
+     devreg:  [0x2C.0x8C,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
+     driver: switch_PS
+     devreg:  [0x2C.0x8D,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+##Local MP per FPGA node
+   - name: UNB2_FPGA_DDR4_SLOT_TEMP
+     description: Signed I2C!
+     driver: switch_DDR4
+     devreg:  [0x18.0x5,0x19.0x5]
+     width: 13
+     rw:  ro
+     dtype: double
+     scale: 0.0625 
+     dim: 16
+     monitor: true
+
+   - name: UNB2_FPGA_DDR4_SLOT_PART_NUMBER
+     driver: switch_DDR4
+     devreg:  [0x18.0x149,0x19.0x149]
+     width: 160
+     rw:  hidden #ro
+     dtype: string
+     dim: 16
+#     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
+     driver: switch_FPGA_PS
+     devreg:  [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 8
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
+     driver: switch_FPGA_PS
+     devreg:  [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 8
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_VOUT]
+     driver: switch_FPGA_PS
+     devreg:  [0x1.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 1.220703125e-4 #2^-13
+     dim: 8
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
+     driver: switch_FPGA_PS
+     devreg:  [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 2.44140625e-4 #2^-12
+     dim: 8
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
+     driver: switch_FPGA_PS
+     devreg:  [0x1.0x20,0xD.0x20,0xE.0x20,0xF.0x20,0x10.0x20,0x11.0x20]
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 8
+     debug: true
+     monitor: true
+
+
+##Local MP per FPGA node, QSFP cage
+   - name: UNB2_FPGA_QSFP_CAGE_TEMP
+     description: Signed I2C!
+     driver: switch_QSFP
+     devreg:  0x50.0x16
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: 3.90625e-3 #1/256
+     dim: 48
+     monitor: true
+
+   - name: UNB2_FPGA_QSFP_CAGE_LOS
+     description: Bits for 4 TX, 4 RX channels
+     driver: switch_QSFP
+     devreg:  0x50.0x03
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 48
+     monitor: true
+
+
+methods:
+  - name: UNB2TR_Init #Called after startup to load. 
+    driver: switch_UNB2
+    debug: True
+    instructions:   
+      - UNB2_EEPROM_Unique_ID: Update
+
+
+  - name: UNB2_on
+    mask: UNB2_mask
+    instructions:
+     - FP_IO.CONF: 0xff    #TODO: setup correctly
+     - UNB2_Front_Panel_LED: 1
+
+  - name: UNB2_off
+    mask: UNB2_mask
+    instructions:
+     - UNB2_Front_Panel_LED: 2

i2cserv/i2c_array2.py

@@ -27,6 +27,7 @@ class i2c_array2(i2c_array):
         self.sw2=[x for x in sw2 for i in range(self.N//len(sw1)//len(sw2))]*len(sw1)
         self.sw3=[x for x in sw3]*len(sw1)*len(sw2)
         logging.debug(str(("Init",config['name'],' len=',self.N,'Nswitch=',self.Nswitch,self.sw1,self.sw2,self.sw3)))
+        self.I2Ccut=3;
 
     def SetSwitch(self,RCUi):
         #print("Set switch element",RCUi,'=',self.sw1[RCUi],self.sw2[RCUi],(self.sw3[RCUi] if len(self.sw3)<0 else 'x'))

opcuaserv/opcuaserv.py

@@ -83,7 +83,7 @@ def InitServer(port=4840):
 # setup our server
     global server,running,PCCobj,DEBUGobj,idx,sub;
     server = Server()
-    server.set_endpoint("opc.tcp://0.0.0.0:{}/PCC/".format(port))
+    server.set_endpoint("opc.tcp://0.0.0.0:{}/".format(port))
 
     idx = server.register_namespace("http://lofar.eu")
 #    uri = "http://examples.freeopcua.github.io"
@@ -92,7 +92,7 @@ def InitServer(port=4840):
     objects = server.get_objects_node()
 
     # populating our address space
-    PCCobj = objects.add_object(idx, "PCC")
+    PCCobj = objects #.add_object(idx, "PCC")
     DEBUGobj = PCCobj.add_object(idx, "DEBUG")
 #    self.PCCobj=PCCobj