Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
P
PyPCC
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
LOFAR2.0
PyPCC
Commits
91caf20b
Commit
91caf20b
authored
4 years ago
by
Paulus Kruger
Browse files
Options
Downloads
Plain Diff
Merge branch 'master' of
https://git.astron.nl/lofar2.0/pypcc
parents
9280211f
99274ae2
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
rcu/RCU.py
+25
-25
25 additions, 25 deletions
rcu/RCU.py
with
25 additions
and
25 deletions
rcu/RCU.py
+
25
−
25
View file @
91caf20b
...
...
@@ -26,7 +26,7 @@ def bytes2int(bts):
return
x
;
def
int2bytes
(
i
):
b
=
[];
while
i
>
255
:
while
i
>
255
:
b
=
[
i
%
256
]
+
b
;
i
>>=
8
;
return
[
i
]
+
b
;
...
...
@@ -95,7 +95,7 @@ class RCU1():
mask
=
0
;
RCU0
=-
1
;
for
RCUi
in
range
(
self
.
N
):
if
(
Mask
[
RCUi
]):
if
(
Mask
[
RCUi
]):
mask
|=
1
<<
Vars
.
RCU_MPaddr
.
Switch
[
RCUi
]
if
RCU0
<
0
:
RCU0
=
RCUi
;
if
RCU0
<
0
:
return
;
#Mask all zero
...
...
@@ -171,7 +171,7 @@ class RCU1():
Step
=
V1
.
nVars
Step2
=
int
(
V1
.
size
/
V1
.
nVars
)
if
V1
.
Vars
[
0
].
type
==
Vars
.
DevType
.
I2C
:
for
Vari
in
range
(
Step
):
for
Vari
in
range
(
Step
):
DevReg
=
V1
.
Vars
[
Vari
].
devreg
self
.
SWcallback
(
mask
)
self
.
SetI2CAddr
(
self
,
DevReg
)
...
...
@@ -191,7 +191,7 @@ class RCU1():
self
.
GetBBValueAll
(
V1
,
value1
,
mask
)
# logging.info("SPIbb all not implemented yet")
elif
V1
.
Vars
[
0
].
type
==
Vars
.
DevType
.
HBA1
:
for
Vari
in
range
(
Step
):
for
Vari
in
range
(
Step
):
var
=
V1
.
Vars
[
Vari
]
# self.SWcallback(mask)
# self.SetI2CAddr(self,DevReg)
...
...
@@ -221,7 +221,7 @@ class RCU1():
def
GetBit
(
RCUixx
,
dev
,
width
,
bitoffset
,
buffer
=
False
):
value
=
[
0
for
RCUi
in
range
(
self
.
N
)]
value2
=
[
0
]
if
buffer
:
if
buffer
:
for
RCUi
in
range
(
self
.
N
):
self
.
GetI2Cbuffer
(
RCUi
,
dev
,
width
,
bitoffset
,
value2
)
value
[
RCUi
]
=
value2
[
0
]
...
...
@@ -279,7 +279,7 @@ class RCU1():
self
.
I2Ccallback
(
0x40
,
XX
,
reg
=
0
,
read
=
1
)
#wakeup, do nothing
self
.
I2Ccallback
(
dev
.
Addr
,[
10
],
read
=
3
)
self
.
I2Ccallback
(
dev
.
Addr
,
value
[:
16
],
reg
=
dev
.
Register_W
)
if
L
>
16
:
if
L
>
16
:
self
.
I2Ccallback
(
dev
.
Addr
,[
10
],
read
=
3
)
self
.
I2Ccallback
(
dev
.
Addr
,
value
[
16
:],
reg
=
dev
.
Register_W
+
16
)
self
.
I2Ccallback
(
dev
.
Addr
,[
600
],
read
=
3
)
#Wait 500ms
...
...
@@ -291,15 +291,15 @@ class RCU1():
value
[
0
]
=
self
.
previous
[
RCUi
,
dev
.
store
-
1
];
# logging.debug(str(("GetI2Cbuffer",RCUi,dev.store,value)))
l1
=
int
(
np
.
floor
((
width
+
bitoffset
+
7
)
/
8
))
if
(
width
!=
l1
*
8
)
or
(
bitoffset
>
0
):
if
(
width
!=
l1
*
8
)
or
(
bitoffset
>
0
):
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
return
True
def
GetI2C
(
self
,
RCUi
,
dev
,
width
,
bitoffset
,
value
):
# if dev.store>0:
# value[0]=self.previous[RCUi,dev.store-1]
# return True
# return True
l1
=
int
(
np
.
floor
((
width
+
bitoffset
+
7
)
/
8
))
# print(width,bitoffset,l1)
makesinglevalue
=
((
len
(
value
)
==
1
)
and
(
l1
>
1
));
...
...
@@ -318,9 +318,9 @@ class RCU1():
if
dev
.
store
>
0
:
self
.
previous
[
RCUi
,
dev
.
store
-
1
]
=
value
[
0
]
# logging.debug(str(("Store buffer",RCUi,dev.store,value[0])))
if
(
width
!=
l1
*
8
)
or
(
bitoffset
>
0
):
if
(
width
!=
l1
*
8
)
or
(
bitoffset
>
0
):
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
else
:
value
[
0
]
=
value2
[
0
]
return
True
;
def
GetI2Cbit
(
self
,
RCUi
,
dev
,
pin
):
...
...
@@ -350,9 +350,9 @@ class RCU1():
# logging.debug(str(("Store buffer",RCUi,dev.store,value[0])))
# if width<8:
if
(
width
!=
l1
*
8
)
or
(
bitoffset
>
0
):
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
# value[0]=UnMask(value[0],width,bitoffset)
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
# value[0]=UnMask(value[0],width,bitoffset)
#else: value[0]=value2[0]
#if (len(value)>1) and (width<8): print value
return
True
;
...
...
@@ -368,8 +368,8 @@ class RCU1():
print
(
"
HBA
"
,
RCUi
,
dev
.
Addr
,
"
received:
"
,
value
);
# if dev.store>0: #This is disabled due to noise on readback
# self.previousHBA[RCUi,dev.store-1]=value[:]
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
for
i
in
range
(
len
(
value
)):
value
[
i
]
=
UnMask
(
value
[
i
],
width
,
bitoffset
)
return
True
;
...
...
@@ -385,15 +385,15 @@ class RCU1():
RCUthread1
=
threading
.
Thread
(
target
=
RCUthread
,
args
=
(
Q1
,))
RCUthread1
.
start
()
return
RCUthread1
return
RCUthread1
def
Queue_Monitor
(
self
,
Q1
,
NRCU
):
Inst1
=
Vars
.
Instr
(
Vars
.
DevType
.
VarUpdate
,
Vars
.
RCU_temp
,
NRCU
,[
0
]
*
NRCU
)
Q1
.
put
(
Inst1
)
Inst1
=
Vars
.
Instr
(
Vars
.
DevType
.
VarUpdate
,
Vars
.
RCU_ADC_lock
,
96
,[
0
]
*
96
)
Q1
.
put
(
Inst1
)
return
Inst1
=
Vars
.
Instr
(
Vars
.
DevType
.
VarUpdate
,
Vars
.
RCU_temp
,
NRCU
,[
0
]
*
NRCU
)
Q1
.
put
(
Inst1
)
Inst1
=
Vars
.
Instr
(
Vars
.
DevType
.
VarUpdate
,
Vars
.
RCU_ADC_lock
,
96
,[
0
]
*
96
)
Q1
.
put
(
Inst1
)
return
def
AddVars
(
self
,
Q1
,
AddVarR
,
AddVarW
,
AddVar
):
self
.
statevar
=
AddVar
(
"
RCU_state_R
"
,
"
busy
"
)
for
v
in
Vars
.
OPC_devvars
:
...
...
@@ -404,7 +404,7 @@ class RCU1():
varvalue2
=
0
if
v
.
type
==
Vars
.
datatype
.
dInt
:
varvalue2
=
dim2
*
[
0
]
elif
v
.
type
==
Vars
.
datatype
.
dbool
:
varvalue2
=
dim2
*
[
False
]
elif
v
.
type
==
Vars
.
datatype
.
dfloat
:
varvalue2
=
dim2
*
[
0.0
]
elif
v
.
type
==
Vars
.
datatype
.
dfloat
:
varvalue2
=
dim2
*
[
0.0
]
elif
v
.
type
==
Vars
.
datatype
.
dstring
:
varvalue2
=
dim1
*
[
"
"
*
dim3
]
print
(
len
(
varvalue2
),
varvalue2
)
if
v
.
RW
in
[
Vars
.
RW
.
ReadOnly
,
Vars
.
RW
.
ReadWrite
]:
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment