ADC preemp, UNB2 monitor only 1 POL

pypcc/config/RECVTR_LB.yaml

@@ -149,6 +149,9 @@ device_registers:
     - name: CML_level
       description: CML output adjust
       address: 0x15
+    - name: PREEM
+      description: Set Preemphasis on with 0x14
+      address: 0xA8
     - name: Update
       description: Global device uptate
       address: 0xFF
@@ -584,6 +587,16 @@ variables:
      dim2: [3,32]
      debug: true
 
+   - name: RCU_ADC_PREEM
+     driver: I2C_RCU
+     devreg:  [ADC1.PREEM,ADC2.PREEM,ADC3.PREEM]
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 96
+     dim2: [3,32]
+     debug: true
+
    - name: RCU_DTH_freq
      description: RCU Dither source frequency (Hz). Should be around 102MHz.
      driver: I2C_RCU
@@ -797,7 +810,8 @@ methods:
     instructions:
      - ADC1.JESD_control1 : 0x14
      - ADC1.SYNC_control: 1  #Setup ADCs
-     - ADC1.CML_level: 0x7
+     - ADC1.CML_level: 0x5 #7
+     - ADC1.PREEM: 0x14 #7
      - ADC1.dither : 0x00
      - ADC1.t1l: 0xff #p1
      - ADC1.t1m: 0x7f
@@ -816,7 +830,8 @@ methods:
     instructions:
      - ADC2.JESD_control1 : 0x14
      - ADC2.SYNC_control: 1  #Setup ADCs
-     - ADC2.CML_level: 0x7
+     - ADC2.CML_level: 0x5 #7
+     - ADC2.PREEM: 0x14 #7
      - ADC2.dither : 0x00
      - ADC2.Update: 1       #Needed to update ADC registers
 
@@ -827,7 +842,8 @@ methods:
     instructions:
      - ADC3.JESD_control1 : 0x14
      - ADC3.SYNC_control: 1  #Setup ADCs
-     - ADC3.CML_level: 0x7
+     - ADC3.CML_level: 0x5 #7
+     - ADC3.PREEM: 0x14 #7
      - ADC3.dither : 0x00
      - ADC3.Update: 1       #Needed to update ADC registers
 

pypcc/config/UNB2TR.yaml

@@ -350,7 +350,7 @@ variables:
      dtype: uint8
      dim: 2
      debug: true
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
      driver: switch_PS
@@ -362,7 +362,7 @@ variables:
      endian: "<"
      scale: 1.220703125e-4 #2^-13
      dim: 2
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
      driver: switch_PS
@@ -376,10 +376,23 @@ variables:
      dim: 2
      monitor: true
 
-   - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+#   - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+   - name: [UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+     driver: switch_PS
+#     devreg:  [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+#     devreg:  [DC_DC.IOUT,POL_QSFP0.IOUT,POL_QSFP1.IOUT,POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
+     devreg:  [POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+   - name: UNB2_DC_DC_48V_12V_IOUT
      driver: switch_PS
 #     devreg:  [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
-     devreg:  [DC_DC.IOUT,POL_QSFP0.IOUT,POL_QSFP1.IOUT,POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
+     devreg:  DC_DC.IOUT 
      width: 16
      rw:  ro
      dtype: double
@@ -387,10 +400,23 @@ variables:
      dim: 2
      monitor: true
 
-   - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
+#   - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
+   - name: [UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
      driver: switch_PS
 #     devreg:  [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
-     devreg:  [DC_DC.TEMP,POL_QSFP0.TEMP,POL_QSFP1.TEMP,POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
+#     devreg:  [DC_DC.TEMP,POL_QSFP0.TEMP,POL_QSFP1.TEMP,POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
+     devreg:  [POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+   - name: UNB2_DC_DC_48V_12V_TEMP 
+     driver: switch_PS
+#     devreg:  DC_DC.TEMP
+     devreg:  DC_DC.TEMP 
      width: 16
      rw:  ro
      dtype: double
@@ -408,7 +434,7 @@ variables:
      scale: 0.0625 
      dim: 16
      dim2: [8,2]
-     monitor: true
+#     monitor: true
 
    - name: UNB2_FPGA_DDR4_SLOT_PART_NUMBER
      driver: switch_DDR4
@@ -430,7 +456,7 @@ variables:
      scale: smbus_2bytes_to_float
      dim: 8
      dim2: [4,2]
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
      driver: switch_FPGA_PS
@@ -442,7 +468,7 @@ variables:
      scale: smbus_2bytes_to_float
      dim: 8
      dim2: [4,2]
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_VOUT]
      driver: switch_FPGA_PS
@@ -454,7 +480,7 @@ variables:
      scale: 1.220703125e-4 #2^-13
      dim: 8
      dim2: [4,2]
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
      driver: switch_FPGA_PS
@@ -467,7 +493,7 @@ variables:
      scale: 2.44140625e-4 #2^-12
      dim: 8
      dim2: [4,2]
-     monitor: true
+#     monitor: true
 
    - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
      driver: switch_FPGA_PS