L2TS phase 1 old APSCT config

pypcc/config/APSCTTR_L2TS1.yaml

+version: "1.0"
+description: "1234"
+
+drivers:
+ - name: I2C
+   type: i2c
+   parameters: [5] #I2C port number
+ - name: I2C_CLK
+   type: i2c_dev #I2C devices
+   parent: I2C
+   status: APSCTTR_I2C_error
+ - name: SPIbb1 
+   type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+   parent: I2C_CLK
+   devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
+   parameters: [4,7,5,6]
+ - name: SPIbb2 
+   type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+   parent: I2C_CLK
+   devreg: [IO2.GPIO1,IO2.GPIO1,IO2.GPIO1,IO2.GPIO1]
+   parameters: [4,7,5,6]
+
+#This is the I2C devices in the RCU
+device_registers:
+ - name: IO
+   dim: 2
+   description: IO-Expander (TCA6416APWR)
+   address: [0x20,0x21]
+   driver: I2C_CLK
+   registers:
+   - name: CONF1
+     description: Direction of port1
+     address: 6
+     store: True
+   - name: CONF2
+     description: Direction of port2
+     address: 7
+     store: True
+   - name: GPIO1
+     description: Input/Ouput port 1
+     address: [0,2]  #Read / Write address different
+     store: True
+   - name: GPIO2
+     description: Input/Ouput port 2
+     address: [1,3]  #Read / Write address different
+     store: True
+
+ - name: PLL2
+   driver: SPIbb1
+   registers:
+    - name: PLL_stat
+      description: PLL locked status
+      address: 0x0
+    - {name: r3, address: 0x03}
+    - {name: r5, address: 0x05}
+    - {name: r6, address: 0x06}
+
+ - name: PLL1
+   driver: SPIbb2
+   registers:
+    - name: PLL_stat
+      description: PLL locked status
+      address: 0x0
+    - {name: r3, address: 0x03}
+    - {name: r5, address: 0x05}
+    - {name: r6, address: 0x06}
+
+ - name: ROM
+   description: 24AA02UIDT
+   address: 0x50
+   driver: I2C_CLK
+   registers:
+   - name: ID
+     description: Random
+     address: 0xfc
+   - name: Version
+     description: Set in production
+     address: 0
+   - name: Serial
+     address: 0x20
+
+ - name: VSENSE
+   description: Monitor ADC
+   address: 0x74
+   device: LTC2495
+   driver: I2C_CLK
+   registers:
+   - name: V_0
+     address: 0xB080
+     wait: 250
+   - name: V_1
+     address: 0xB880
+     wait: 250
+   - name: V_2
+     address: 0xB180
+     wait: 250
+   - name: V_3
+     address: 0xB980
+     wait: 250
+   - name: V_4
+     address: 0xB280
+     wait: 250
+   - name: V_5
+     address: 0xBA80
+     wait: 250
+   - name: V_6
+     address: 0xB380
+     wait: 250
+   - name: Temp
+     address: 0xA0C0
+     wait: 250
+
+
+variables:
+  - name: APSCTTR_I2C_error
+    description: 0=good, >0 indicates an I2C communication error
+    driver: I2C_CLK
+    rw:  ro #server RW variable, not linked to IO
+    dtype: uint8
+
+  - name: APSCTTR_monitor_rate
+    description: Monitor rate in seconds
+    rw:  variable 
+    dtype: uint8
+
+  - name: APSCTTR_translator_busy
+    description: True when I2C line busy
+    rw:  ro #server variable, not linked to IO
+    dtype: boolean
+    dim: 1
+
+  - name: APSCT_PCB_ID
+    description: Unique PCB ID
+    driver: I2C_CLK
+    devreg:  ROM.ID
+    width: 32
+    rw:  ro
+    dtype: uint32
+
+  - name: APSCT_PCB_version
+    description: Version number
+    driver: I2C_CLK
+    devreg:  ROM.Version
+    width: 0x80  #16 characters
+    rw:  ro
+    dtype: string
+
+  - name: APSCT_PCB_number
+    description: PCB number (astron.nl/webforms/IenS-Boarden/view.php?id=xxx)
+    driver: I2C_CLK
+    devreg:  ROM.Serial
+    width: 0x80  #16 characters
+    rw:  ro
+    dtype: string
+
+
+  - name: [APSCT_PWR_PLL_200MHz_on,APSCT_PWR_PLL_160MHz_on]
+    description: CLK power status. Controlled by APSCT_xxxMHz_ON and APSCT_OFF
+    rw:  ro
+    dtype: boolean
+    driver: I2C_CLK
+    devreg:  [IO1.GPIO1,IO2.GPIO1]
+    bitoffset: 1
+    width: 1
+
+  - name: APSCT_PWR_on
+    description: CLK power status. Controlled by APSCT_xxxMHz_ON and APSCT_OFF
+    rw:  ro
+    dtype: boolean
+    driver: I2C_CLK
+    devreg:  IO1.GPIO2
+    bitoffset: 3
+    width: 1
+
+  - name: APSCT_PPS_ignore
+    rw:  rw
+    dtype: boolean
+    driver: I2C_CLK
+    devreg:  IO1.GPIO2
+    bitoffset: 2
+    width: 1
+
+  - name: [APSCT_INPUT_10MHz_good,APSCT_INPUT_PPS_good]
+    rw:  ro
+    dtype: boolean
+    driver: I2C_CLK
+    devreg:  IO2.GPIO2
+    bitoffset: [0,1]
+    width: 1
+    monitor: true
+
+
+  - name: [APSCT_PLL_200MHz_locked,APSCT_PLL_160MHz_locked]
+#    description: First status pin give lock status
+    rw:  ro
+    dtype: boolean
+    monitor: true
+    driver: I2C_CLK
+    devreg:  [IO1.GPIO1,IO2.GPIO1]
+    bitoffset: 2
+    width: 1
+
+  - name: [APSCT_PLL_200MHz_error,APSCT_PLL_160MHz_error]
+#    description: Second status pin give error
+    rw:  ro
+    dtype: boolean
+    monitor: true
+    driver: I2C_CLK
+    devreg:  [IO1.GPIO1,IO2.GPIO1]
+    bitoffset: 3
+    width: 1
+
+  - name: APSCT_PLL_200MHz_locked_SPI
+    description: 0x81=locked
+    driver: I2C_CLK
+    devreg:  PLL2.PLL_stat
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+  - name: APSCT_PLL_160MHz_locked_SPI
+    description: 0x81=locked
+    driver: I2C_CLK
+    devreg:  PLL1.PLL_stat
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+#  - name: [APSCT_PLL_r3,APSCT_PLL_r5,APSCT_PLL_r6]
+#    driver: I2C_CLK
+#    devreg:  [PLL.r3,PLL.r5,PLL.r6]
+#    width: 8
+#    rw:  ro
+#    dtype: uint8
+#    debug: True
+
+  - name: [APSCT_IO1_GPIO1,APSCT_IO1_GPIO2,APSCT_IO2_GPIO1,APSCT_IO2_GPIO2]
+    driver: I2C_CLK
+    devreg:  [IO1.GPIO1,IO1.GPIO2,IO2.GPIO1,IO2.GPIO2]
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+  - name: APSCT_IO2_GPIO1
+    driver: I2C_CLK
+    devreg:  IO2.GPIO1
+    width: 8
+    rw:  ro
+    dtype: uint8
+    debug: True
+
+  - name: APSCT_TEMP
+    description: Temperature sensor on PCB
+    driver: I2C_CLK
+    devreg:  VSENSE.Temp
+    width: 23
+    scale: 3.8265e-3
+    convert_unit: Kelvin2Celsius
+    rw:  ro
+    dtype: double
+    monitor: true
+
+  - name: [APSCT_PWR_INPUT_3V3,APSCT_PWR_PLL_160MHz_3V3,APSCT_PWR_PLL_200MHz_3V3,APSCT_PWR_CLKDIST1_3V3,APSCT_PWR_CLKDIST2_3V3,APSCT_PWR_PPSDIST_3V3,APSCT_PWR_CTRL_3V3]
+    driver: I2C_CLK
+    devreg:  [VSENSE.V_0,VSENSE.V_1,VSENSE.V_2,VSENSE.V_3,VSENSE.V_4,VSENSE.V_5,VSENSE.V_6]
+    width: 23
+    scale: 1.12165e-6
+    rw:  ro
+    dtype: double
+    monitor: true
+
+
+methods:
+  - name: APSCTTR_Init #Called after startup to load. Should have all stored registers  
+    driver: I2C_CLK
+    debug: True
+    instructions:   
+      - APSCTTR_I2C_error : 0
+      - APSCT_IO1_GPIO1 : Update
+      - APSCT_IO1_GPIO2 : Update
+      - APSCT_IO2_GPIO1 : Update
+      - APSCT_IO2_GPIO2 : Update
+      - IO1.CONF1: Update
+      - IO1.CONF2: Update
+      - IO2.CONF1: Update
+      - IO2.CONF2: Update
+      - APSCTTR_Update: 0
+
+  - name: APSCTTR_Update
+    driver: I2C_CLK
+    debug: True
+    instructions:   
+      - APSCT_PCB_ID : Update
+      - APSCT_PCB_version : Update
+      - APSCT_PCB_number : Update
+      - APSCT_PWR_on: Update
+      - APSCT_PWR_PLL_200MHz_on: Update
+      - APSCT_PLL_200MHz_locked: Update
+      - APSCT_PLL_200MHz_error: Update
+      - APSCT_PWR_PLL_160MHz_on: Update
+      - APSCT_PLL_160MHz_locked: Update
+      - APSCT_PLL_160MHz_error: Update
+      - APSCT_PPS_ignore : Update
+
+  - name: APSCT_200MHz_on  
+    driver: I2C_CLK
+    description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
+    instructions:   
+     - APSCTTR_I2C_error : 0
+     - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO1.CONF2: 0x00 
+     - IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO2.CONF2: 0x03 #
+     - IO1.GPIO1: 0x42 #0100 0010 high:200MHz PLL enable, CS high
+     - IO1.GPIO2: 0xF8 #PWR enable  ##Check if not 4??
+     - IO2.GPIO1: 0x00 #All low
+     - IO2.GPIO2: 0x00 #All low (just inputs)
+
+     - WAIT: 200        
+     - APSCT_PLL200_setup: 0
+     - WAIT: 200         #ms to wait before checking lock
+     - APSCTTR_Update: 0   #refresh all settings
+
+  - name: APSCT_160MHz_on  
+    driver: I2C_CLK
+    description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
+    instructions:   
+     - APSCTTR_I2C_error : 0
+     - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO1.CONF2: 0x00 
+     - IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+     - IO2.CONF2: 0x03 #
+     - IO1.GPIO1: 0x00      
+     - IO1.GPIO2: 0x08 #PWR enable  ##Check if not 4??
+     - IO2.GPIO1: 0x42 #0100 0010 high:160MHz PLL enable, CS high
+     - IO2.GPIO2: 0x00 #All low (just inputs)
+
+     - WAIT: 200        
+     - APSCT_PLL160_setup: 0
+     - WAIT: 200         #ms to wait before checking lock
+     - APSCTTR_Update: 0   #refresh all settings
+
+  - name: APSCT_off  
+    driver: I2C_CLK
+    description: Switch clock off. Monitored using APSCT_PWR_on
+    instructions:   
+     - APSCTTR_I2C_error : 0
+     - IO1.GPIO1: 0x00
+     - IO1.GPIO2: 0x00 
+     - IO2.GPIO1: 0x00 
+     - IO2.GPIO2: 0x00 
+     - APSCTTR_Update: 0   #refresh all settings
+
+  - name: APSCT_PLL200_setup  
+    driver: I2C_CLK
+    debug: true
+    instructions:   
+#   - PLL2.0x03: 0x08 #Set power, this is default
+    - PLL2.0x04: 0xCF #
+    - PLL2.0x05: 0x97 #was 97, set lock time = =x17?
+    - PLL2.0x06: 0x10
+
+    - PLL2.0x07: 0x04 #Stop R divider
+    - PLL2.0x08: 0x01 #Set R divider
+    - PLL2.0x07: 0x00 #Start R divider
+
+    - PLL2.0x09: 0x10 #Stop N divider
+    - PLL2.0x0A: 0x14 #Set N divider=20, 200MHz/20=10MHz = input clock
+    - PLL2.0x09: 0x00 #Start N divider
+
+    - PLL2.0x0D: 0x01 #Divider output 1=1 
+    - PLL2.0x0F: 0x01 #Divider output 2=1
+    - PLL2.0x11: 0x01 #Divider output 3=1
+    - PLL2.0x13: 0x01 #Divider output 4=1
+
+  - name: APSCT_PLL160_setup  
+    driver: I2C_CLK
+    debug: true
+    instructions:   
+#   - PLL1.0x03: 0x08 #Set power, this is default
+    - PLL1.0x04: 0xCF #
+    - PLL1.0x05: 0x97 #was 97, set lock time = =x17?
+    - PLL1.0x06: 0x10
+
+    - PLL1.0x07: 0x04 #Stop R divider
+    - PLL1.0x08: 0x01 #Set R divider
+    - PLL1.0x07: 0x00 #Start R divider
+
+    - PLL1.0x09: 0x10 #Stop N divider
+    - PLL1.0x0A: 0x10 #Set N divider=16, 160MHz/16=10MHz = input clock
+    - PLL1.0x09: 0x00 #Start N divider
+
+    - PLL1.0x0D: 0x01 #Divider output 1=1 
+    - PLL1.0x0F: 0x01 #Divider output 2=1
+    - PLL1.0x11: 0x01 #Divider output 3=1
+    - PLL1.0x13: 0x01 #Divider output 4=1
+
+
+

pypcc/config/UNB2TR_L2TS1.yaml

+version: "0.0"
+description: "UNB2 DTS first draft" 
+
+drivers:
+ - name: I2C1
+   type: i2c_switch2 
+   devreg: [APSCT_SWITCH.MASK,UB2_SWITCH1.MASK,UB2_SWITCH2.MASK] 
+   parameters: [3,0,0,0] #I2C port number, 3x switch reset pins 
+
+ - name: switch_UNB2
+   type: i2c_array
+   parent: I2C1
+   parameters: [0,1] #lookup table
+   I2Ccut: 10
+   status: UNB2TR_I2C_bus_error
+
+ - name: switch_PS
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  4,4] 
+   status: UNB2TR_I2C_bus_PS_error
+
+ - name: switch_FP
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  5,5] 
+   status: UNB2TR_I2C_bus_FP_error
+
+ - name: switch_QSFP 
+   type: i2c_array2 #An array of similar devices connected to an I2C switch
+   parent: I2C1
+   parameters: [0,1,  0,3,  0,3, 6,7] #Parameters: APSCT_Switch, main switch, 2nd switch, 2nd switch
+   status: UNB2TR_I2C_bus_QSFP_error
+
+ - name: switch_DDR4
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  0,3,  4,4]
+   status: UNB2TR_I2C_bus_DDR4_error
+
+ - name: switch_FPGA_PS
+   type: i2c_array2 
+   parent: I2C1
+   parameters: [0,1,  0,3,  5,5] 
+   status: UNB2TR_I2C_bus_FPGA_PS_error
+
+ - name: GPIO
+   type: gpio
+   parameters: [19,26] 
+
+ - name: I2C_GPIO
+   type: gpio
+   parameters: [11,13] 
+
+  
+#This is the I2C devices in the RCU
+device_registers:
+- name: APSCT_SWITCH #not in LTS
+  description: Uniboard select switch on APSCT
+  address: 0x70
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+- name: UB2_SWITCH1
+  description: UNB2 primary switch
+  address: 0x71
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+- name: UB2_SWITCH2
+  description: UNB2 secondary switch
+  address: 0x72
+  device: TCA9548
+  driver: I2C1
+  registers:
+  - name: MASK
+
+- name: FP_IO
+  description: IO-Expander for front panel
+  address: 0x41
+  device: PCA9536
+  driver: switch_FP
+  registers:
+  - name: CONF #default 0xff = all input
+    description: Direction of GPIO
+    address: 3
+  - name: GPIO
+    description: Input/Ouput port 
+    address: [0,1]  #Read / Write address different
+    store: True
+
+
+- name: DC_DC
+  address: 0x2C
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_CORE
+  address: 0x1
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_ERAM
+  address: 0xD
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_RXGXB
+  address: 0xE
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_TXGXB
+  address: 0xF
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_HGXB
+  address: 0x10
+  driver: I2C_switch2
+  registers: 
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_PGM
+  address: 0x11
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_QSFP0
+  address: 0x2
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_QSFP1
+  address: 0x1
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SW1V2
+  address: 0xF
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SWPHY
+  address: 0xE
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_CLOCK
+  address: 0xD
+  driver: I2C_switch2
+  registers:
+  - { name: "TEMP", address: 0x8D, crc: True}
+  - { name: "VIN" , address: 0x88, crc: True}
+  - { name: "VOUT", address: 0x8B, crc: True}
+  - { name: "IOUT", address: 0x8C, crc: True}
+
+variables:
+
+#When I2C bus timeout, bus_error set to False.  Can we set to True again to retry.
+   - name: UNB2TR_I2C_bus_error
+     driver: switch_UNB2
+     rw:  ro
+     dtype: uint8
+     dim: 2
+   - name: UNB2TR_I2C_bus_FP_error
+     driver: switch_UNB2
+     rw:  hidden
+     dtype: uint8
+     dim: 2
+   - name: UNB2TR_I2C_bus_QSFP_error
+     driver: switch_QSFP
+     rw:  ro
+     dtype: uint8
+     dim: 48
+     dim2: [24,2]
+   - name: UNB2TR_I2C_bus_DDR4_error
+     driver: switch_QSFP
+     rw:  ro
+     dtype: uint8
+     dim: 8
+     dim2: [4,2]
+   - name: UNB2TR_I2C_bus_FPGA_PS_error
+     driver: switch_FPGA_PS
+     rw:  ro
+     dtype: uint8
+     dim: 8
+     dim2: [4,2]
+   - name: UNB2TR_I2C_bus_PS_error
+     driver: switch_PS
+     rw:  ro
+     dtype: uint8
+     dim: 2
+
+   - name: UNB2TR_monitor_rate
+     description: Monitor rate in seconds
+     rw:  variable 
+     dtype: uint8
+
+   - name: UNB2TR_translator_busy
+     description: False when idle
+     rw:  ro #server variable, not linked to IO
+     dtype: boolean
+
+##Central MP for whole Uniboard2
+   - name: UNB2_mask
+     rw:  variable #translator variable
+     dtype: boolean
+     dim: 2
+
+   - name: UNB2_PWR_on
+     driver: GPIO
+     mask: UNB2_mask
+     width: 1
+     rw:  ro
+     dtype: boolean
+     convert_unit: bool_invert
+     dim: 2
+
+   - name: UNB2_I2C_enabled
+     driver: I2C_GPIO
+     mask: UNB2_mask
+     width: 1
+     rw:  ro
+     dtype: boolean
+     dim: 2
+
+   - name: UNB2_Front_Panel_LED_colour
+     description: bit 0=Red, 1=Blue, 2=Green
+     mask: UNB2_mask
+     driver: switch_FP
+     devreg: FP_IO.GPIO
+#     bitoffset: 4
+     width: 3
+     rw:  rw
+     dtype: uint8
+     dim: 2
+
+   - name: UNB2_PCB_version
+     driver: switch_UNB2
+     devreg: 0x50.0
+     width: 0x80 #16 char
+     rw:  ro
+     dtype: string
+     dim: 2
+
+   - name: UNB2_PCB_number
+     description: PCB number (astron.nl/webforms/IenS-Boarden/view.php?id=xxx)
+     driver: switch_UNB2
+     devreg:  0x50.0x20
+     width: 0x80  #16 characters
+     rw:  ro
+     dtype: string
+     dim: 2
+
+   - name: UNB2_PCB_ID
+     driver: switch_UNB2
+     devreg: 0x50.0xFC
+     width: 32
+     rw:  ro
+     dtype: uint32
+     dim: 2
+
+
+   - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT]
+     driver: switch_PS
+     devreg:  [DC_DC.VIN,DC_DC.VOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 4.8828125e-4 #2^-11
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_VOUT_MODE,UNB2_POL_QSFP_N01_VOUT_MODE,UNB2_POL_QSFP_N23_VOUT_MODE,UNB2_POL_SWITCH_1V2_VOUT_MODE,UNB2_POL_SWITCH_PHY_VOUT_MODE,UNB2_POL_CLOCK_VOUT_MODE]
+     driver: switch_PS
+     devreg:  [0x2C.0x20,0x2.0x20,0x1.0x20,0xF.0x20,0xE.0x20,0xD.0x20]
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 2
+     debug: true
+     monitor: true
+
+   - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
+     driver: switch_PS
+#     devreg:  [0x2.0x8B,0x1.0x8B]
+     devreg:  [POL_QSFP0.VOUT,POL_QSFP1.VOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 1.220703125e-4 #2^-13
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
+     driver: switch_PS
+#     devreg:  [0xF.0x8B,0xE.0x8B,0xD.0x8B]
+     devreg:  [POL_SW1V2.VOUT,POL_SWPHY.VOUT,POL_CLOCK.VOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 2.44140625e-4 #2^-12
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+     driver: switch_PS
+#     devreg:  [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+     devreg:  [DC_DC.IOUT,POL_QSFP0.IOUT,POL_QSFP1.IOUT,POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+   - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
+     driver: switch_PS
+#     devreg:  [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+     devreg:  [DC_DC.TEMP,POL_QSFP0.TEMP,POL_QSFP1.TEMP,POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 2
+     monitor: true
+
+##Local MP per FPGA node
+   - name: UNB2_FPGA_DDR4_SLOT_TEMP
+     driver: switch_DDR4
+     devreg:  [0x18.0x5,0x19.0x5]
+     width: 13
+     rw:  ro
+     dtype: double
+     scale: 0.0625 
+     dim: 16
+     dim2: [8,2]
+     monitor: true
+
+   - name: UNB2_FPGA_DDR4_SLOT_PART_NUMBER
+     driver: switch_DDR4
+     devreg:  [0x18.0x149,0x19.0x149]
+     width: 160
+     rw:  hidden #ro
+     dtype: string
+     dim: 16
+     dim2: [8,2]
+#     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
+     driver: switch_FPGA_PS
+#     devreg:  [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+     devreg:  [POL_CORE.IOUT,POL_ERAM.IOUT,POL_RXGXB.IOUT,POL_TXGXB.IOUT,POL_HGXB.IOUT,POL_PGM.IOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 8
+     dim2: [4,2]
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
+     driver: switch_FPGA_PS
+#     devreg:  [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
+     devreg:  [POL_CORE.TEMP,POL_ERAM.TEMP,POL_RXGXB.TEMP,POL_TXGXB.TEMP,POL_HGXB.TEMP,POL_PGM.TEMP]
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: smbus_2bytes_to_float
+     dim: 8
+     dim2: [4,2]
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_VOUT]
+     driver: switch_FPGA_PS
+     devreg:  [POL_CORE.VOUT]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 1.220703125e-4 #2^-13
+     dim: 8
+     dim2: [4,2]
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
+     driver: switch_FPGA_PS
+     devreg:  [POL_ERAM.VOUT,POL_RXGXB.VOUT,POL_TXGXB.VOUT,POL_HGXB.VOUT,POL_PGM.VOUT]
+#     devreg:  [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
+     width: 16
+     rw:  ro
+     dtype: double
+     endian: "<"
+     scale: 2.44140625e-4 #2^-12
+     dim: 8
+     dim2: [4,2]
+     monitor: true
+
+   - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
+     driver: switch_FPGA_PS
+     devreg:  [0x1.0x20,0xD.0x20,0xE.0x20,0xF.0x20,0x10.0x20,0x11.0x20]
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 8
+     dim2: [4,2]
+     debug: true
+#     monitor: true
+
+
+##Local MP per FPGA node, QSFP cage
+   - name: UNB2_FPGA_QSFP_CAGE_TEMP
+     driver: switch_QSFP
+     devreg:  0x50.0x16
+     width: 16
+     rw:  ro
+     dtype: double
+     scale: 3.90625e-3 #1/256
+     convert_unit: temp_check
+     dim: 48
+     dim2: [24,2]
+     monitor: true
+
+   - name: UNB2_FPGA_QSFP_CAGE_LOS
+     description: Bits for 4 TX, 4 RX channels
+     driver: switch_QSFP
+     devreg:  0x50.0x03
+     width: 8
+     rw:  ro
+     dtype: uint8
+     dim: 48
+     dim2: [24,2]
+     monitor: true
+
+methods:
+  - name: UNB2TR_Init #Called after startup to load. 
+    driver: switch_UNB2
+    debug: True
+    instructions:   
+      - UNB2TR_I2C_error: 0
+      - UNB2_I2C_enabled: 1 #Make sure I2C switches are enabled
+      - UNB2_PCB_ID: Update
+      - UNB2_PCB_version: Update
+      - UNB2_PCB_number: Update
+#      - FP_IO.CONF: 0xf8 #bit 0-2 output for LED
+      - UNB2_Front_Panel_LED_colour: Update
+      - UNB2_PWR_on: Update
+
+  - name: UNB2_on
+    mask: UNB2_mask
+    driver: switch_FP
+    instructions:
+     - UNB2_I2C_enabled: 1 #Make sure I2C switches are enabled
+     - FP_IO.CONF: 0xf8 #bit 0-2 output for LED
+     - UNB2_PWR_on: 0 #already inverted
+     - UNB2_Front_Panel_LED_colour: 3 #green
+     - UNB2_PCB_ID: Update
+     - UNB2_PCB_version: Update
+     - WAIT: 5000         
+
+  - name: UNB2_off
+    mask: UNB2_mask
+    instructions:
+     - UNB2_PWR_on: 1 #inverted
+     - WAIT: 5000         
+#     - UNB2_Front_Panel_LED_colour: 2