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ddr_testdriver.vhd 26.99 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tech_ddr_component_pkg.all;
-- This module instantiates the Altera MegaWizard DDR3 controller and
-- test driver for both modules.
-- It adds a control state machine so the Nios can offload the task of
-- monitoring the test progress.
-- Nov 13th 2014
-- name changed to ddr_testdriver
-- added generic for technology independance
-- added support for DDR4 in Arria10
-- parameterise bus widths
ENTITY ddr_testdriver IS
generic (
g_SELECT_MODULE : IN INTEGER := 5 -- 0 for original guess using 'normal' high peed controller,
-- 1 for Micron MT4JSF12864HZ-1G4D1 at 800MT/s using high speed controller II
-- 2 for Micron MT4JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II
-- 3 for Micron MT8JSF12864HZ-1G4D1 at 800MT/s using high speed controller II
-- 4 for Micron MT8JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II
-- 5 for Micron MT16JSF51264HZ-1G4D1 at 1066MT/s using high speed controller II
-- 6 for Micron MT8JSF12864HZ-1G4D1 at 1066MT/s using high speed controller II with bitwise pnf
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
reset_n : IN STD_LOGIC; -- active low reset
-- SO-DIMM Memory Bank I
MB_I_EVENT : IN STD_LOGIC;
MB_I_DQ : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0);
MB_I_A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MB_I_BA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
MB_I_DQS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_I_DQS_N : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_I_DM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_I_CAS : OUT STD_LOGIC;
MB_I_RAS : OUT STD_LOGIC;
MB_I_WE : OUT STD_LOGIC;
MB_I_RESET : OUT STD_LOGIC;
MB_I_ODT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_I_CK : INOUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_I_CK_N : INOUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_I_CKE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); MB_I_S : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_I_SCL : OUT STD_LOGIC;
MB_I_SDA : INOUT STD_LOGIC;
-- SO-DIMM Memory Bank II
MB_II_EVENT : IN STD_LOGIC;
MB_II_DQ : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0);
MB_II_A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MB_II_BA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
MB_II_DQS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_II_DQS_N : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_II_DM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MB_II_CAS : OUT STD_LOGIC;
MB_II_RAS : OUT STD_LOGIC;
MB_II_WE : OUT STD_LOGIC;
MB_II_RESET : OUT STD_LOGIC;
MB_II_ODT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_II_CK : INOUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_II_CK_N : INOUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_II_CKE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_II_S : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MB_II_SCL : OUT STD_LOGIC;
MB_II_SDA : INOUT STD_LOGIC;
-- avalon MM control interface
mm_clock : in std_logic;
mm_writedata : in std_logic_vector(31 downto 0);
mm_readdata : out std_logic_vector(31 downto 0);
mm_write : in std_logic;
mm_address : in std_logic_vector(2 downto 0)
);
END ddr_testdriver;
architecture archi of ddr_testdriver is
component ddr3_test_example_top_special_hsII1066_MT8 is
port (
-- inputs:
signal clock_source : IN STD_LOGIC;
signal global_reset_n : IN STD_LOGIC;
signal start_test : IN STD_LOGIC;
-- outputs:
signal mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
signal mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal mem_cas_n : OUT STD_LOGIC;
signal mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_clk : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal mem_clk_n : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_dm : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_dq : INOUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_dqs : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_dqsn : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_ras_n : OUT STD_LOGIC;
signal mem_reset_n : OUT STD_LOGIC;
signal mem_we_n : OUT STD_LOGIC;
signal pnf : OUT STD_LOGIC;
signal pnf_per_byte : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pnf_per_bit : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal data_per_bit : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal test_complete : OUT STD_LOGIC;
signal test_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
type driver_state_type is (
IDLE,
START_TEST,
WAIT_FOR_TEST,
STOP_ON_ERROR
);
-- Signals for controlling the tests
signal driver_state_I : driver_state_type;
signal driver_state_II : driver_state_type;
signal control : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal itercount_I : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal itercount_II : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal testtimeout_I : STD_LOGIC;
signal testtimeout_II : STD_LOGIC;
signal timeoutcount_I : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal timeoutcount_II : STD_LOGIC_VECTOR (15 DOWNTO 0);
-- signal to generate delays before initialising the modules
signal delay_count : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal delayed_resetn_I : STD_LOGIC;
signal delayed_resetn_II: STD_LOGIC;
-- signals for controlling the tests
signal pnf_I_d1 : STD_LOGIC := '0';
signal pnf_I_d2 : STD_LOGIC := '0';
signal pnf_II_d1 : STD_LOGIC := '0';
signal pnf_II_d2 : STD_LOGIC := '0';
signal test_complete_I_d1 : STD_LOGIC := '0';
signal test_complete_I_d2 : STD_LOGIC := '0';
signal test_complete_II_d1 : STD_LOGIC := '0';
signal test_complete_II_d2 : STD_LOGIC := '0';
signal start_test_I : STD_LOGIC := '0';
signal start_test_II : STD_LOGIC := '0';
signal test_complete_I : STD_LOGIC;
signal test_complete_II : STD_LOGIC;
signal test_status_I : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal test_status_II : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pnf_I : STD_LOGIC;
signal pnf_II : STD_LOGIC;
signal pnfperbyte_I : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pnfperbyte_II : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pnfperbit_I : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"00000000";
signal pnfperbit_II : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"00000000";
signal dataperbit_I : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"00000000";
signal dataperbit_II : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"00000000";
signal fsm_I : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fsm_II : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin
-- Avalon MM control registers
mm_interface: process(mm_clock)
variable arp_timeout_count : integer := 0;
begin
if mm_clock'event and mm_clock = '1' then
if mm_write = '1' then
case mm_address is
when "000" =>
control <= mm_writedata;
when others =>
end case;
else
case mm_address is
when "001" => mm_readdata <= test_status_I & X"0000" & "00" & fsm_I &"00" & testtimeout_I & pnf_I_d2;
when "010" =>
mm_readdata <= itercount_I(31 downto 0);
when "011" =>
mm_readdata <= itercount_I(63 downto 32);
when "100" =>
mm_readdata <= test_status_II & X"0000" & "00" & fsm_II &"00" & testtimeout_II & pnf_II_d2;
when "101" =>
mm_readdata <= itercount_II(31 downto 0);
when "110" =>
mm_readdata <= itercount_II(63 downto 32);
when others =>
mm_readdata <= X"ffffffff";
end case;
end if;
end if;
end process;
-- Test control process
test_control_I: process(mm_clock)
begin
if mm_clock'event and mm_clock = '1' then
if reset_n = '0' then
driver_state_I <= IDLE;
driver_state_II <= IDLE;
itercount_I <= (others => '0');
itercount_II <= (others => '0');
pnf_I_d1 <= '0';
pnf_I_d2 <= '0';
pnf_II_d1 <= '0';
pnf_II_d2 <= '0';
test_complete_I_d1 <= '0';
test_complete_I_d2 <= '0';
test_complete_II_d1 <= '0';
test_complete_II_d2 <= '0';
else
-- reclock the control signals from the phy clock domains
pnf_I_d1 <= pnf_I;
pnf_I_d2 <= pnf_I_d1;
pnf_II_d1 <= pnf_II;
pnf_II_d2 <= pnf_II_d1;
test_complete_I_d1 <= test_complete_I;
test_complete_I_d2 <= test_complete_I_d1;
test_complete_II_d1 <= test_complete_II;
test_complete_II_d2 <= test_complete_II_d1;
case driver_state_I is
when IDLE =>
fsm_I <= "00";
if control(0) = '1' then
itercount_I <= (others => '0');
driver_state_I <= START_TEST;
end if;
when START_TEST =>
fsm_I <= "01";
start_test_I <= '1';
timeoutcount_I <= (others => '0');
testtimeout_I <= '0';
driver_state_I <= WAIT_FOR_TEST;
when WAIT_FOR_TEST =>
fsm_I <= "10";
timeoutcount_I <= timeoutcount_I + 1;
if timeoutcount_I = X"000F" then
start_test_I <= '0';
end if;
if timeoutcount_I = X"FFFF" then
testtimeout_I <= '1';
driver_state_I <= STOP_ON_ERROR; end if;
if test_complete_I_d2 = '1' then
if pnf_I_d2 = '1' then
if control(0) = '1' then
driver_state_I <= START_TEST;
itercount_I <= itercount_I + 1;
else
driver_state_I <= IDLE;
end if;
else
driver_state_I <= STOP_ON_ERROR;
end if;
end if;
when STOP_ON_ERROR =>
fsm_I <= "11";
if control(0) = '0' then
driver_state_I <= IDLE;
end if;
when others =>
driver_state_I <= IDLE;
end case;
case driver_state_II is
when IDLE =>
fsm_II <= "00";
if control(1) = '1' then
itercount_II <= (others => '0');
driver_state_II <= START_TEST;
end if;
when START_TEST =>
fsm_II <= "01";
start_test_II <= '1';
timeoutcount_II <= (others => '0');
testtimeout_II <= '0';
driver_state_II <= WAIT_FOR_TEST;
when WAIT_FOR_TEST =>
fsm_II <= "10";
timeoutcount_II <= timeoutcount_II + 1;
if timeoutcount_II = X"000F" then
start_test_II <= '0';
end if;
if timeoutcount_II = X"FFFF" then
testtimeout_II <= '1';
driver_state_II <= STOP_ON_ERROR;
end if;
if test_complete_II_d2 = '1' then
if PNF_II_d2 = '1' then
if control(1) = '1' then
driver_state_II <= START_TEST;
itercount_II <= itercount_II + 1;
else
driver_state_II <= IDLE;
end if;
else
driver_state_II <= STOP_ON_ERROR;
end if;
end if;
when STOP_ON_ERROR =>
fsm_II <= "11";
if control(1) = '0' then
driver_state_II <= IDLE;
end if;
when others =>
driver_state_II <= IDLE;
end case;
end if;
end if;
end process;
-- instantiate the DDR3 test generator examples depending on the chosen module
hsIgen: if g_SELECT_MODULE = 0 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_I_A(14 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE,
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S,
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT,
mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
ddr3_test_II : ddr3_test_example_top_runonce
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_II_A(14 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE,
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S,
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT,
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
end GENERATE hsIgen;
hsII800gen: if g_SELECT_MODULE = 1 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce_hsII800
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_I_A(13 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE,
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S,
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT,
mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
ddr3_test_II : ddr3_test_example_top_runonce_hsII800
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_II_A(13 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE,
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S,
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT,
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
end GENERATE hsII800gen;
hsII1066gen: if g_SELECT_MODULE = 2 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce_hsII1066
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_I_A(13 downto 0),
mem_ba => MB_I_BA, mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE,
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S,
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT,
mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
ddr3_test_II : ddr3_test_example_top_runonce_hsII1066
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_II_A(13 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE,
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S,
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT,
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
end GENERATE hsII1066gen;
hsII800MT8gen: if g_SELECT_MODULE = 3 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce_hsII800_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_I_A(13 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE(0 downto 0),
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S(0 downto 0),
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT(0 downto 0), mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
MB_I_CKE(1) <= '0';
MB_I_S(1) <= '0';
MB_I_ODT(1) <= '0';
ddr3_test_II : ddr3_test_example_top_runonce_hsII800_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => reset_n,
-- outputs:
mem_addr => MB_II_A(13 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE(0 downto 0),
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S(0 downto 0),
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT(0 downto 0),
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
MB_II_CKE(1) <= '0';
MB_II_S(1) <= '0';
MB_II_ODT(1) <= '0';
end GENERATE hsII800MT8gen;
hsII1066MT8gen: if g_SELECT_MODULE = 4 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce_hsII1066_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_I,
-- outputs:
mem_addr => MB_I_A(13 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE(0 downto 0),
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S(0 downto 0),
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT(0 downto 0),
mem_ras_n => MB_I_RAS, mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
MB_I_CKE(1) <= '0';
MB_I_S(1) <= '0';
MB_I_ODT(1) <= '0';
ddr3_test_II : ddr3_test_example_top_runonce_hsII1066_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_II,
-- outputs:
mem_addr => MB_II_A(13 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE(0 downto 0),
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S(0 downto 0),
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT(0 downto 0),
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
MB_II_CKE(1) <= '0';
MB_II_S(1) <= '0';
MB_II_ODT(1) <= '0';
end GENERATE hsII1066MT8gen;
hsII1066MT16gen: if g_SELECT_MODULE = 5 GENERATE
ddr3_test_I : ddr3_test_example_top_runonce_hsII1066_MT16
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_I,
-- outputs:
mem_addr => MB_I_A(14 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE,
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S,
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT,
mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET, mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
ddr3_test_II : ddr3_test_example_top_runonce_hsII1066_MT16
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_II,
-- outputs:
mem_addr => MB_II_A(14 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE,
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S,
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT,
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
end GENERATE hsII1066MT16gen;
hsII1066MT8specgen: if g_SELECT_MODULE = 6 GENERATE
ddr3_test_I : ddr3_test_example_top_special_hsII1066_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_I,
-- outputs:
mem_addr => MB_I_A(13 downto 0),
mem_ba => MB_I_BA,
mem_cas_n => MB_I_CAS,
mem_cke => MB_I_CKE(0 downto 0),
mem_clk => MB_I_CK ,
mem_clk_n => MB_I_CK_N,
mem_cs_n => MB_I_S(0 downto 0),
mem_dm => MB_I_DM,
mem_dq => MB_I_DQ,
mem_dqs => MB_I_DQS ,
mem_dqsn => MB_I_DQS_N,
mem_odt => MB_I_ODT(0 downto 0),
mem_ras_n => MB_I_RAS,
mem_reset_n => MB_I_RESET,
mem_we_n => MB_I_WE,
pnf => pnf_I,
pnf_per_byte => pnfperbyte_I,
pnf_per_bit => pnfperbit_I,
data_per_bit => dataperbit_I,
start_test => start_test_I,
test_complete => test_complete_I,
test_status => test_status_I
);
MB_I_CKE(1) <= '0';
MB_I_S(1) <= '0';
MB_I_ODT(1) <= '0';
ddr3_test_II : ddr3_test_example_top_special_hsII1066_MT8
port map(
-- inputs:
clock_source => CLK,
global_reset_n => delayed_resetn_II,
-- outputs:
mem_addr => MB_II_A(13 downto 0),
mem_ba => MB_II_BA,
mem_cas_n => MB_II_CAS,
mem_cke => MB_II_CKE(0 downto 0),
mem_clk => MB_II_CK ,
mem_clk_n => MB_II_CK_N,
mem_cs_n => MB_II_S(0 downto 0),
mem_dm => MB_II_DM,
mem_dq => MB_II_DQ,
mem_dqs => MB_II_DQS ,
mem_dqsn => MB_II_DQS_N,
mem_odt => MB_II_ODT(0 downto 0),
mem_ras_n => MB_II_RAS,
mem_reset_n => MB_II_RESET,
mem_we_n => MB_II_WE,
pnf => pnf_II,
pnf_per_byte => pnfperbyte_II,
pnf_per_bit => pnfperbit_II,
data_per_bit => dataperbit_II,
start_test => start_test_II,
test_complete => test_complete_II,
test_status => test_status_II
);
MB_II_CKE(1) <= '0';
MB_II_S(1) <= '0';
MB_II_ODT(1) <= '0';
end GENERATE hsII1066MT8specgen;
delay_proc : process(mm_clock)
begin
if rising_edge(mm_clock)then
if reset_n = '0' then
delay_count <= (others => '0');
delayed_resetn_I <= '0';
delayed_resetn_II <= '0';
else
if delayed_resetn_II = '0' then -- stop counter after module II enabled
delay_count <= delay_count + 1;
end if;
if delay_count = X"4C4B40" then -- 100ms
-- if delay_count = X"4C" then
delayed_resetn_I <= '1';
end if;
if delay_count = X"989680" then -- 200ms
-- if delay_count = X"4C" then
delayed_resetn_II <= '1';
end if;
end if;
end if;
end process;
end archi;