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HWconf.py

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    HWconf.py 3.56 KiB
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    from collections import namedtuple
from enum import Enum

#Mid plane address
MPaddr=namedtuple("MPaddr","nI2C I2C nSwitch Switch"); 
RCU_MPaddr=MPaddr(1,[1],32,[1,2,3,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5])
CLK_MPaddr=MPaddr(1,[1],1,[7])

DevReg=namedtuple("DevReg","Addr Register_R Register_W store"); 
#I2C:Addr=I2C addr (int)
#BBdev: Addr=BBdev (pointer)

#Control board switch
#dev: TCA9548
SW1_ch=DevReg(0x70,0,0,0) 
#I2C IO-Expanders
#Device: TCA9539
RCU_IO1_OUT1=DevReg(0x75,0,2,1)
RCU_IO1_OUT2=DevReg(0x75,1,3,2)
RCU_IO1_CONF1=DevReg(0x75,6,6,3)
RCU_IO1_CONF2=DevReg(0x75,7,7,4)
#Device: TCA9539
RCU_IO2_OUT1=DevReg(0x76,0,2,5)
RCU_IO2_OUT2=DevReg(0x76,1,3,6)
RCU_IO2_CONF1=DevReg(0x76,6,6,7)
RCU_IO2_CONF2=DevReg(0x76,7,7,8)
#Device: TCA6416
RCU_IO3_OUT1=DevReg(0x20,0,2,9)
RCU_IO3_OUT2=DevReg(0x20,1,3,10)
RCU_IO3_CONF1=DevReg(0x20,6,6,11)
RCU_IO3_CONF2=DevReg(0x20,7,7,12)

RCU_storeReg=13; #Number of stored registers

#I2C monitor ADC
RCU_AN_Ch0=DevReg(0x14,0xB080,-1,0)
RCU_AN_Ch1=DevReg(0x14,0xB880,-1,0)
RCU_AN_Ch2=DevReg(0x14,0xB180,-1,0)
#etc
RCU_AN_Temp=DevReg(0x14,0xA0C0,-1,0)

#Bitbang devices
BBdev=namedtuple("BBdev","nPins devs pins addr")
I2CBB_dth3=BBdev(3,[RCU_IO1_OUT1,RCU_IO2_OUT2,RCU_IO2_CONF2],[6,3,3],0x70); #SCL,SDIO,SDIOdir
I2CBB_dth2=BBdev(3,[RCU_IO1_OUT2,RCU_IO2_OUT1,RCU_IO1_CONF1],[7,7,7],0x70);
I2CBB_dth1=BBdev(3,[RCU_IO1_OUT2,RCU_IO2_OUT1,RCU_IO1_CONF1],[7,7,7],0x70);
SPIBB_ADC1=BBdev(4,[RCU_IO3_OUT1,RCU_IO3_OUT1,RCU_IO3_CONF1,RCU_IO3_OUT2],[1,0,0,0],0) #CLK,SDIO,SDIOdir,CS
SPIBB_ADC2=BBdev(4,[RCU_IO3_OUT1,RCU_IO3_OUT1,RCU_IO3_CONF1,RCU_IO3_OUT2],[3,2,2,1],0) #CLK,SDIO,SDIOdir,CS
SPIBB_ADC3=BBdev(4,[RCU_IO3_OUT1,RCU_IO3_OUT1,RCU_IO3_CONF1,RCU_IO3_OUT2],[5,4,4,2],0) #CLK,SDIO,SDIOdir,CS

#SPI ADC 
#Dev: AD9683 
RCU_ADC1_PLL_stat =DevReg(SPIBB_ADC1,0X0A,0X0A,0) # PLL locked status
RCU_ADC1_JESD_ctr =DevReg(SPIBB_ADC1,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC1_CML_level=DevReg(SPIBB_ADC1,0X15,0X15,0) #CML output adjust
RCU_ADC1_SYNC_ctr =DevReg(SPIBB_ADC1,0X3A,0X3A,0) #SYNC / SYSREF control
RCU_ADC1_update   =DevReg(SPIBB_ADC1,0XFF,0xFF,0)    # Global device update

RCU_ADC2_PLL_stat =DevReg(SPIBB_ADC2,0X0A,0X0A,0) # PLL locked status
RCU_ADC2_JESD_ctr =DevReg(SPIBB_ADC2,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC2_CML_level=DevReg(SPIBB_ADC2,0X15,0X15,0) #CML output adjust
RCU_ADC2_SYNC_ctr =DevReg(SPIBB_ADC2,0X3A,0X3A,0) #SYNC / SYSREF control
RCU_ADC2_update   =DevReg(SPIBB_ADC2,0XFF,0xFF,0)    # Global device update

RCU_ADC3_PLL_stat =DevReg(SPIBB_ADC3,0X0A,0X0A,0) # PLL locked status
RCU_ADC3_JESD_ctr =DevReg(SPIBB_ADC3,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC3_CML_level=DevReg(SPIBB_ADC3,0X15,0X15,0) #CML output adjust
RCU_ADC3_SYNC_ctr =DevReg(SPIBB_ADC3,0X3A,0X3A,0) #SYNC / SYSREF control
RCU_ADC3_update   =DevReg(SPIBB_ADC3,0XFF,0xFF,0)    # Global device update

#I2C_dither 
#Dev: SI4010
RCU_Dth1_Freq =DevReg(I2CBB_dth1,0x1140,0x1141,0) ##TBC
RCU_Dth1_Prop =DevReg(I2CBB_dth1,0x11  ,0x11,0) 
RCU_Dth1_Start=DevReg(I2CBB_dth1,0x62  ,0x62,0) 
RCU_Dth1_Stop =DevReg(I2CBB_dth1,0x67  ,0x67,0) 
RCU_Dth2_Freq =DevReg(I2CBB_dth2,0x1140,0x1141,0) ##TBC
RCU_Dth2_Prop =DevReg(I2CBB_dth2,0x11  ,0x11,0) 
RCU_Dth2_Start=DevReg(I2CBB_dth2,0x62  ,0x62,0) 
RCU_Dth2_Stop =DevReg(I2CBB_dth2,0x67  ,0x67,0) 
RCU_Dth3_Freq =DevReg(I2CBB_dth3,0x1140,0x1141,0) ##TBC
RCU_Dth3_Prop =DevReg(I2CBB_dth3,0x11  ,0x11,0) 
RCU_Dth3_Start=DevReg(I2CBB_dth3,0x62  ,0x62,0) 
RCU_Dth3_Stop =DevReg(I2CBB_dth3,0x67  ,0x67,0) 

class DevType(Enum):
    Var = 0
    I2C  = 1
    SPIbb= 2
    I2Cbb= 3
    Instr =4
    VarUpdate = 5
    Internal = 6