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CentralLogger.py

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    ddrctrl_input_repack.vhd 8.64 KiB
    -------------------------------------------------------------------------------
    --
    -- Copyright 2022
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- Licensed under the Apache License, Version 2.0 (the "License");
    -- you may not use this file except in compliance with the License.
    -- You may obtain a copy of the License at
    --
    --     http://www.apache.org/licenses/LICENSE-2.0
    --
    -- Unless required by applicable law or agreed to in writing, software
    -- distributed under the License is distributed on an "AS IS" BASIS,
    -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    -- See the License for the specific language governing permissions and
    -- limitations under the License.
    --
    -------------------------------------------------------------------------------
    -- Author: Job van Wee
    -- Purpose: Resize the input data vector so that the output data vector can be
    --  stored into the ddr memory.
    --
    -- Description:
    --  The input data gets resized and put into the output data vector.
    --
    -- Remark:
    --  Use VHDL coding template from:
    --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
    --  The output vector must be larger than the input vector.
    
    library IEEE, dp_lib, tech_ddr_lib;
    use IEEE.std_logic_1164.all;
    use dp_lib.dp_stream_pkg.all;
    use tech_ddr_lib.tech_ddr_pkg.all;
    
    entity ddrctrl_input_repack is
      generic (
        g_tech_ddr              : t_c_tech_ddr;  -- type of memory
        g_in_data_w             : natural       := 168;  -- the input data with
        g_bim                   : natural;
        g_of_pb                 : natural;
        g_block_size            : natural
      );
      port (
        clk                     : in  std_logic;
        rst                     : in  std_logic;
        in_sosi                 : in  t_dp_sosi;  -- input data
        in_stop                 : in  std_logic := '0';
        out_sosi                : out t_dp_sosi := c_dp_sosi_init;  -- output data
        out_bsn_wr              : out std_logic := '0';
        out_data_stopped        : out std_logic := '0'
      );
    end ddrctrl_input_repack;
    
    architecture rtl of ddrctrl_input_repack is
      -- constant for readability
      constant c_out_data_w     : natural       := func_tech_ddr_ctlr_data_w( g_tech_ddr );  -- the output data with, 576
      constant k_c_v_w          : natural       := c_out_data_w * 2;  -- the c_v data with, 2*576=1152
    
      -- type for statemachine
      type t_state is (OVERFLOW_OUTPUT, FILL_VECTOR, FIRST_OUTPUT, RESET, STOP, BSN);
    
      -- record for readability
      type t_reg is record
      state                     : t_state;  -- the state the process is currently in;
      c_v                       : std_logic_vector(k_c_v_w - 1 downto 0);  -- the vector that stores the input data until the data is put into the output data vector
      c_v_count                 : natural;  -- the amount of times the c_v vector received data from the input since the last time it was filled completely
      q_bsn                     : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
      q_sop                     : std_logic;