Reinier van der Walle
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
    out_sosi.valid <= mm_miso.rdval;  -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
    out_sosi.sop   <= out_sop;        -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
    out_sosi.eop   <= out_eop;        -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+    out_sosi.sync  <= out_sync;       -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sync can be used for output sync
+    out_sosi.bsn(g_bsn_w-1 DOWNTO 0)  <= out_bsn;  -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.bsn can be used for output bsn