Merge branch 'master' into L2SDP-390

applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl

applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE qsys_lofar2_unb2c_ddrctrl_pkg IS
+
+    ----------------------------------------------------------------------
+    -- this component declaration is copy-pasted from Quartus QSYS builder
+    ----------------------------------------------------------------------
+
+    component qsys_lofar2_unb2c_ddrctrl is
+        port (
+            avs_eth_0_reset_export                 : out std_logic;                                        -- export
+            avs_eth_0_clk_export                   : out std_logic;                                        -- export
+            avs_eth_0_tse_address_export           : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_tse_write_export             : out std_logic;                                        -- export
+            avs_eth_0_tse_read_export              : out std_logic;                                        -- export
+            avs_eth_0_tse_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_tse_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_tse_waitrequest_export       : in  std_logic                     := 'X';             -- export
+            avs_eth_0_reg_address_export           : out std_logic_vector(3 downto 0);                     -- export
+            avs_eth_0_reg_write_export             : out std_logic;                                        -- export
+            avs_eth_0_reg_read_export              : out std_logic;                                        -- export
+            avs_eth_0_reg_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reg_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_ram_address_export           : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_ram_write_export             : out std_logic;                                        -- export
+            avs_eth_0_ram_read_export              : out std_logic;                                        -- export
+            avs_eth_0_ram_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_ram_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_irq_export                   : in  std_logic                     := 'X';             -- export
+            clk_clk                                : in  std_logic                     := 'X';             -- clk
+            reset_reset_n                          : in  std_logic                     := 'X';             -- reset_n
+            pio_pps_reset_export                   : out std_logic;                                        -- export
+            pio_pps_clk_export                     : out std_logic;                                        -- export
+            pio_pps_address_export                 : out std_logic_vector(1 downto 0);                     -- export
+            pio_pps_write_export                   : out std_logic;                                        -- export
+            pio_pps_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
+            pio_pps_read_export                    : out std_logic;                                        -- export
+            pio_pps_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_system_info_reset_export           : out std_logic;                                        -- export
+            pio_system_info_clk_export             : out std_logic;                                        -- export
+            pio_system_info_address_export         : out std_logic_vector(4 downto 0);                     -- export
+            pio_system_info_write_export           : out std_logic;                                        -- export
+            pio_system_info_writedata_export       : out std_logic_vector(31 downto 0);                    -- export
+            pio_system_info_read_export            : out std_logic;                                        -- export
+            pio_system_info_readdata_export        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_wdi_external_connection_export     : out std_logic;                                        -- export
+            ram_scrap_reset_export                 : out std_logic;                                        -- export
+            ram_scrap_clk_export                   : out std_logic;                                        -- export
+            ram_scrap_address_export               : out std_logic_vector(8 downto 0);                     -- export
+            ram_scrap_write_export                 : out std_logic;                                        -- export
+            ram_scrap_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
+            ram_scrap_read_export                  : out std_logic;                                        -- export
+            ram_scrap_readdata_export              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_ctrl_reset_export             : out std_logic;                                        -- export
+            reg_dpmm_ctrl_clk_export               : out std_logic;                                        -- export
+            reg_dpmm_ctrl_address_export           : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_ctrl_write_export             : out std_logic;                                        -- export
+            reg_dpmm_ctrl_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_ctrl_read_export              : out std_logic;                                        -- export
+            reg_dpmm_ctrl_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_data_reset_export             : out std_logic;                                        -- export
+            reg_dpmm_data_clk_export               : out std_logic;                                        -- export
+            reg_dpmm_data_address_export           : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_data_write_export             : out std_logic;                                        -- export
+            reg_dpmm_data_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_data_read_export              : out std_logic;                                        -- export
+            reg_dpmm_data_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_epcs_reset_export                  : out std_logic;                                        -- export
+            reg_epcs_clk_export                    : out std_logic;                                        -- export
+            reg_epcs_address_export                : out std_logic_vector(2 downto 0);                     -- export
+            reg_epcs_write_export                  : out std_logic;                                        -- export
+            reg_epcs_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
+            reg_epcs_read_export                   : out std_logic;                                        -- export
+            reg_epcs_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_temp_sens_reset_export        : out std_logic;                                        -- export
+            reg_fpga_temp_sens_clk_export          : out std_logic;                                        -- export
+            reg_fpga_temp_sens_address_export      : out std_logic_vector(2 downto 0);                     -- export
+            reg_fpga_temp_sens_write_export        : out std_logic;                                        -- export
+            reg_fpga_temp_sens_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_temp_sens_read_export         : out std_logic;                                        -- export
+            reg_fpga_temp_sens_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_voltage_sens_reset_export     : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_clk_export       : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_address_export   : out std_logic_vector(3 downto 0);                     -- export
+            reg_fpga_voltage_sens_write_export     : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_voltage_sens_read_export      : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_reset_export             : out std_logic;                                        -- export
+            reg_mmdp_ctrl_clk_export               : out std_logic;                                        -- export
+            reg_mmdp_ctrl_address_export           : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_ctrl_write_export             : out std_logic;                                        -- export
+            reg_mmdp_ctrl_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_ctrl_read_export              : out std_logic;                                        -- export
+            reg_mmdp_ctrl_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_data_reset_export             : out std_logic;                                        -- export
+            reg_mmdp_data_clk_export               : out std_logic;                                        -- export
+            reg_mmdp_data_address_export           : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_data_write_export             : out std_logic;                                        -- export
+            reg_mmdp_data_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_data_read_export              : out std_logic;                                        -- export
+            reg_mmdp_data_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_remu_reset_export                  : out std_logic;                                        -- export
+            reg_remu_clk_export                    : out std_logic;                                        -- export
+            reg_remu_address_export                : out std_logic_vector(2 downto 0);                     -- export
+            reg_remu_write_export                  : out std_logic;                                        -- export
+            reg_remu_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
+            reg_remu_read_export                   : out std_logic;                                        -- export
+            reg_remu_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_reset_export                   : out std_logic;                                        -- export
+            reg_wdi_clk_export                     : out std_logic;                                        -- export
+            reg_wdi_address_export                 : out std_logic_vector(0 downto 0);                     -- export
+            reg_wdi_write_export                   : out std_logic;                                        -- export
+            reg_wdi_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
+            reg_wdi_read_export                    : out std_logic;                                        -- export
+            reg_wdi_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            rom_system_info_reset_export           : out std_logic;                                        -- export
+            rom_system_info_clk_export             : out std_logic;                                        -- export
+            rom_system_info_address_export         : out std_logic_vector(12 downto 0);                    -- export
+            rom_system_info_write_export           : out std_logic;                                        -- export
+            rom_system_info_writedata_export       : out std_logic_vector(31 downto 0);                    -- export
+            rom_system_info_read_export            : out std_logic;                                        -- export
+            rom_system_info_readdata_export        : in  std_logic_vector(31 downto 0) := (others => 'X')  -- export
+        );
+    end component qsys_lofar2_unb2c_ddrctrl;
+
+END qsys_lofar2_unb2c_ddrctrl_pkg;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd

@@ -62,7 +62,7 @@ ENTITY ddrctrl IS
     in_sosi_arr       : IN  t_dp_sosi_arr;                                                                                    -- input data
     stop_in           : IN  STD_LOGIC                                       := '0';
 
-    out_sosi_arr      : OUT t_dp_sosi_arr;
+    out_sosi_arr      : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)         := (OTHERS => c_dp_sosi_rst);
     out_siso          : IN  t_dp_siso                                       := c_dp_siso_rst; 
 
     term_ctrl_out     : OUT   t_tech_ddr3_phy_terminationcontrol;
@@ -235,6 +235,7 @@ BEGIN
   -- reading ddr memory
   u_ddrctrl_output : ENTITY work.ddrctrl_output
   GENERIC MAP(
+    g_technology              => g_technology,
     g_tech_ddr                => g_tech_ddr,
     g_sim_model               => g_sim_model,
     g_in_data_w               => c_io_ddr_data_w,

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -86,7 +86,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
 
   CONSTANT  c_bitshift_w      : NATURAL                                     := ceil_log2(g_burstsize);                        -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
   CONSTANT  c_adr_w           : NATURAL                                     := func_tech_ddr_ctlr_address_w( g_tech_ddr );    -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
-  CONSTANT  c_pof_ma          : NATURAL                                     := (((g_max_adr*(100-g_stop_percentage))/100)/g_adr_per_b)*g_adr_per_b;
+  CONSTANT  c_pof_ma          : NATURAL                                     := (((g_max_adr*(100-g_stop_percentage))/100)/g_adr_per_b)*g_adr_per_b;  --percentage of max address.
 
   CONSTANT  c_zeros           : STD_LOGIC_VECTOR(c_bitshift_w-1 DOWNTO 0)   := (OTHERS => '0');
 
@@ -233,10 +233,10 @@ BEGIN
 
     WHEN SET_STOP =>
       -- this state sets a stop address dependend on the g_stop_percentage.
-      IF inp_adr+c_pof_ma >= g_max_adr THEN
-        v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
+      IF inp_adr-c_pof_ma >= 0 THEN
+        v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w);
       ELSE
-        v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
+        v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w);
       END IF;
       v.ready_for_set_stop                                        := '0';
       v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w)       := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd

@@ -129,7 +129,7 @@ BEGIN
 
 
     WHEN IDLE =>
-    -- after a reset skip the first data block so the ddr memory can initialize.
+    -- after a reset wait for a sop so the memory will be filled with whole blocks.
     IF in_sosi.sop = '1' THEN
       v.bsn_passed := '1';
     END IF;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd

@@ -41,6 +41,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY ddrctrl_output IS
   GENERIC (
+    g_technology      : NATURAL;
     g_tech_ddr        : t_c_tech_ddr;                                                               -- type of memory
     g_sim_model       : BOOLEAN                                     := TRUE;                        -- determens if this is a simulation
     g_in_data_w       : NATURAL                                     := 576;
@@ -66,8 +67,21 @@ ARCHITECTURE str OF ddrctrl_output IS
   -- constant for readability
   CONSTANT  c_out_data_w  : NATURAL     := g_nof_streams*g_data_w;                                    -- the input data width for ddrctrl_repack 168
 
+  -- fifo
+  CONSTANT  c_fifo_size   : NATURAL     := 2;
+
+
   -- signals for connecting the components
   SIGNAL    sosi              : t_dp_sosi := c_dp_sosi_init;
+  SIGNAL    out_sosi          : t_dp_sosi := c_dp_sosi_init;
+--  SIGNAL    out_sosi          : t_dp_sosi := c_dp_sosi_init;
+--  SIGNAL    fifo_snk_in_sosi  : t_dp_sosi := c_dp_sosi_init;
+  SIGNAL    q_out_siso        : t_dp_siso := c_dp_siso_rst;
+  SIGNAL    q_q_out_siso      : t_dp_siso := c_dp_siso_rst;
+  SIGNAL    unpack_state_off  : STD_LOGIC := '0';
+--  SIGNAL    siso              : t_dp_siso := c_dp_siso_rst;
+--  SIGNAL    fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
+--  SIGNAL    fifo_usedw        : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0)  := (OTHERS => '0');
 
 BEGIN
 
@@ -86,8 +100,9 @@ BEGIN
     in_sosi           => in_sosi,                                                                       -- input data
     in_bsn            => in_bsn,
     out_siso          => out_siso,
-    out_sosi          => sosi,                                                                      -- output data
-    out_ready         => out_ready
+    out_sosi          => out_sosi,                                                                      -- output data
+    out_ready         => out_ready,
+    state_off         => unpack_state_off
   );
 
   -- resizes the input data vector so that the output data vector can be stored into the ddr memory
@@ -101,4 +116,61 @@ BEGIN
     out_sosi_arr      => out_sosi_arr
   );
 
+
+--  u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+--  GENERIC MAP (
+--    g_technology        => g_technology,
+--    g_wr_data_w         => c_out_data_w,
+--    g_rd_data_w         => c_out_data_w,
+--    g_use_ctrl          => FALSE,
+--    g_wr_fifo_size      => c_fifo_size,
+--    g_wr_fifo_af_margin => 0,
+--    g_rd_fifo_rl        => 0
+--  )
+--  PORT MAP (
+--    wr_rst         => rst,
+--    wr_clk         => clk,
+--    rd_rst         => rst,
+--    rd_clk         => clk,
+--
+--    snk_out        => OPEN,
+--    snk_in         => fifo_snk_in_sosi,
+--  
+--    wr_ful         => OPEN,
+--    wr_usedw       => fifo_usedw,
+--    rd_usedw       => OPEN,
+--    rd_emp         => OPEN,
+--
+--    src_in         => siso,
+--    src_out        => fifo_src_out_sosi
+--  );
+
+
+  p_out_siso_ready : PROCESS(out_siso, clk, out_sosi, q_out_siso)
+
+  VARIABLE sosi_valid : STD_LOGIC := '0';
+
+  BEGIN
+
+    IF out_siso.ready = '0' AND NOT (q_out_siso.ready = out_siso.ready) THEN
+      sosi              <= out_sosi;
+      sosi_valid        := '0';
+      -- assert false report "sosi.valid = '0'" severity note;
+    ELSIF q_out_siso.ready = '1' AND NOT (q_q_out_siso.ready = q_out_siso.ready) AND unpack_state_off = '0' THEN
+      sosi              <= out_sosi;
+      sosi_valid        := '1';
+      -- assert false report "sosi.valid = '1'" severity note;
+    ELSE
+      sosi              <= out_sosi;
+      sosi_valid        := out_sosi.valid;
+    END IF;
+    IF rising_edge(clk) THEN
+      q_q_out_siso        <= q_out_siso;
+      q_out_siso          <= out_siso;
+    END IF;
+    sosi.valid  <= sosi_valid;
+    sosi.sop    <= sosi_valid AND out_sosi.sop;
+    sosi.eop    <= sosi_valid AND out_sosi.eop;
+  END PROCESS;
+
 END str;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd

@@ -156,17 +156,17 @@ BEGIN
   -- generating clock
   clk               <= NOT clk OR tb_end AFTER c_clk_period/2;
   mm_clk            <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
-  out_siso.ready    <= '1';
   out_siso.xon      <= '1';
 
   -- excecuting test
   p_test : PROCESS
 
-
+  VARIABLE  out_siso_ready  : NATURAL := 0;
 
   BEGIN
 
     -- start the test
+    out_siso.ready        <= '1';
     tb_end                <= '0';
     in_sosi_arr(0).valid  <= '0';
     WAIT UNTIL rising_edge(clk);                                                                                                  -- align to rising edge
@@ -205,11 +205,29 @@ BEGIN
           in_sosi_arr(I).data(g_data_w-1 DOWNTO 0)   <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
           in_sosi_arr(I).valid <= '1';
         END LOOP;
+
         IF K = 0 AND J = c_bim*g_block_size-1 THEN
           stop_in <= '1';
         ELSE
           stop_in <= '0';
         END IF;
+
+        FOR L IN 0 TO 30 LOOP
+          IF k = 1 AND J = c_bim*g_block_size*85/100+60+L THEN
+            out_siso_ready := out_siso_ready+1;
+          END IF;
+          IF k = 1 AND J = c_bim*g_block_size*85/100+160+L THEN
+            out_siso_ready := out_siso_ready+1;
+          END IF;
+        END LOOP;
+
+        IF out_siso_ready = 0 THEN
+          out_siso.ready  <= '1';
+        ELSE
+          out_siso.ready  <= '0';
+          out_siso_ready  := 0;
+        END IF;
+
         WAIT FOR c_clk_period*1;
       END LOOP;
     END LOOP;