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RTSD
HDL
Commits
e7ad1bae
Commit
e7ad1bae
authored
10 years ago
by
Jonathan Hargreaves
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progress with unb2_test design
parent
8445de1b
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boards/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf
+68
-1
68 additions, 1 deletion
...s/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf
boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+168
-290
168 additions, 290 deletions
boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
with
236 additions
and
291 deletions
boards/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf
+
68
−
1
View file @
e7ad1bae
...
...
@@ -1569,6 +1569,73 @@ set_location_assignment PIN_J37 -to "RING_1_RX[0](n)"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_xonoff.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pipeline.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_shiftreg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_tail_remove.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_to_mm.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hdr_remove.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_frame_remove.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pad_insert.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_ctlr.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy_reg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui_align_dly.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_gap.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui_framer.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_nonbonded/tb/vhdl/deserializer.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_nonbonded/tb/vhdl/serializer.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/tb/vhdl/sim_xaui.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_mem_mux.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/reconfig_soft.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/phy_xaui_soft.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/phy_xaui_2.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/phy_xaui_1.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/ip/megawizard/phy_xaui_0.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/phy_xaui.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_10GbE/src/ip/megawizard/mac_10g/mac_10g.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_sc.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ready.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_split.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pad_remove.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_input.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_concat.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_from_mm_reg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_cr_cw_ratio.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_from_mm.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/mms_dp_ram_from_mm.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hdr_insert.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_dc.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_dc.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/transceiver/tech_transceiver_arria10_48.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_spulse.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/diagnostics_reg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_mon.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_rx_seq.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_tx_seq.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_block_gen.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/diagnostics.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_lfsr_sequences_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/mms_diagnostics.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/technology_select_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/technology_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../../../libraries/io/node_unb_tr_10GbE/src/vhdl/node_unb_tr_10GbE.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd
...
...
This diff is collapsed.
Click to expand it.
boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+
168
−
290
View file @
e7ad1bae
...
...
@@ -20,11 +20,18 @@
--
-------------------------------------------------------------------------------
LIBRARY
IEEE
,
unb_
common_lib
;
LIBRARY
IEEE
,
common
_lib
,
unb_common_lib
,
diagnostics_lib
,
dp_lib
,
tr_xaui_lib
,
tr_10GbE_lib
,
technology_lib
,
tech_memory
_lib
;
use
unb_common_lib
.
unb_common_pkg
.
all
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
ieee
.
std_logic_arith
.
all
;
use
ieee
.
std_logic_unsigned
.
all
;
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
unb_common_lib
.
unb_common_pkg
.
ALL
;
USE
tr_xaui_lib
.
tr_xaui_pkg
.
ALL
;
USE
dp_lib
.
dp_stream_pkg
.
ALL
;
USE
technology_lib
.
technology_select_pkg
.
ALL
;
USE
technology_lib
.
technology_pkg
.
ALL
;
ENTITY
unb2_test
IS
...
...
@@ -180,69 +187,6 @@ architecture str of unb2_test is
);
end
component
ddr4
;
component
transceiver_phy
is
port
(
tx_analogreset
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_analogreset
tx_digitalreset
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_digitalreset
rx_analogreset
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- rx_analogreset
rx_digitalreset
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- rx_digitalreset
tx_cal_busy
:
out
std_logic_vector
(
47
downto
0
);
-- tx_cal_busy
rx_cal_busy
:
out
std_logic_vector
(
47
downto
0
);
-- rx_cal_busy
rx_is_lockedtodata
:
out
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- rx_is_lockedtodata
tx_serial_clk0
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- clk
rx_cdr_refclk0
:
in
std_logic
:
=
'X'
;
-- clk
tx_serial_data
:
out
std_logic_vector
(
47
downto
0
);
-- tx_serial_data
rx_serial_data
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- rx_serial_data
tx_coreclkin
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- clk
rx_coreclkin
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- clk
tx_clkout
:
out
std_logic_vector
(
47
downto
0
);
-- clk
rx_clkout
:
out
std_logic_vector
(
47
downto
0
);
-- clk
tx_enh_data_valid
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_enh_data_valid
rx_enh_data_valid
:
out
std_logic_vector
(
47
downto
0
);
-- rx_enh_data_valid
rx_enh_blk_lock
:
out
std_logic_vector
(
47
downto
0
);
-- rx_enh_blk_lock
tx_parallel_data
:
in
std_logic_vector
(
3071
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_parallel_data
tx_control
:
in
std_logic_vector
(
383
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_control
tx_err_ins
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_err_ins
unused_tx_parallel_data
:
in
std_logic_vector
(
3071
downto
0
)
:
=
(
others
=>
'X'
);
-- unused_tx_parallel_data
unused_tx_control
:
in
std_logic_vector
(
431
downto
0
)
:
=
(
others
=>
'X'
);
-- unused_tx_control
rx_parallel_data
:
out
std_logic_vector
(
3071
downto
0
);
-- rx_parallel_data
rx_control
:
out
std_logic_vector
(
383
downto
0
);
-- rx_control
unused_rx_parallel_data
:
out
std_logic_vector
(
3071
downto
0
);
-- unused_rx_parallel_data
unused_rx_control
:
out
std_logic_vector
(
575
downto
0
)
-- unused_rx_control
);
end
component
transceiver_phy
;
component
transceiver_reset_controller
is
port
(
clock
:
in
std_logic
:
=
'X'
;
-- clk
reset
:
in
std_logic
:
=
'X'
;
-- reset
pll_powerdown
:
out
std_logic_vector
(
0
downto
0
);
-- pll_powerdown
tx_analogreset
:
out
std_logic_vector
(
47
downto
0
);
-- tx_analogreset
tx_digitalreset
:
out
std_logic_vector
(
47
downto
0
);
-- tx_digitalreset
tx_ready
:
out
std_logic_vector
(
47
downto
0
);
-- tx_ready
pll_locked
:
in
std_logic_vector
(
0
downto
0
)
:
=
(
others
=>
'X'
);
-- pll_locked
pll_select
:
in
std_logic_vector
(
0
downto
0
)
:
=
(
others
=>
'X'
);
-- pll_select
tx_cal_busy
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- tx_cal_busy
rx_analogreset
:
out
std_logic_vector
(
47
downto
0
);
-- rx_analogreset
rx_digitalreset
:
out
std_logic_vector
(
47
downto
0
);
-- rx_digitalreset
rx_ready
:
out
std_logic_vector
(
47
downto
0
);
-- rx_ready
rx_is_lockedtodata
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
);
-- rx_is_lockedtodata
rx_cal_busy
:
in
std_logic_vector
(
47
downto
0
)
:
=
(
others
=>
'X'
)
-- rx_cal_busy
);
end
component
transceiver_reset_controller
;
component
transceiver_pll
is
port
(
pll_powerdown
:
in
std_logic
:
=
'X'
;
-- pll_powerdown
pll_refclk0
:
in
std_logic
:
=
'X'
;
-- clk
pll_locked
:
out
std_logic
;
-- pll_locked
pll_cal_busy
:
out
std_logic
;
-- pll_cal_busy
mcgb_rst
:
in
std_logic
:
=
'X'
;
-- mcgb_rst
mcgb_serial_clk
:
out
std_logic
-- clk
);
end
component
transceiver_pll
;
component
system_pll
is
port
(
...
...
@@ -255,7 +199,7 @@ architecture str of unb2_test is
);
end
component
system_pll
;
component
unb2_
pinning
_qsys
is
component
unb2_
test
_qsys
is
port
(
clk_clk
:
in
std_logic
:
=
'X'
;
-- clk
reset_reset_n
:
in
std_logic
:
=
'X'
;
-- reset_n
...
...
@@ -316,11 +260,15 @@ architecture str of unb2_test is
pio_0_external_connection_export
:
in
std_logic_vector
(
10
downto
0
)
:
=
(
others
=>
'X'
)
-- export
);
end
component
unb2_
pinning
_qsys
;
end
component
unb2_
test
_qsys
;
-- constants
constant
cs_sim
:
std_logic
:
=
'0'
;
constant
cs_sync
:
std_logic
:
=
'1'
;
--CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
CONSTANT
c_block_len
:
NATURAL
:
=
1118
;
-- = 8944 user bytes. Including packetizing: 9012 bytes.
type
t_mem_mosi_arr
is
array
(
0
to
2
)
of
t_mem_mosi
;
type
t_mem_miso_arr
is
array
(
0
to
2
)
of
t_mem_miso
;
-- general reset and clock signals
signal
reset_n
:
std_logic
:
=
'0'
;
...
...
@@ -361,50 +309,42 @@ architecture str of unb2_test is
signal
local_ii_read_data_valid
:
std_logic
;
signal
mb_ii_a_internal
:
std_logic_vector
(
16
downto
0
);
-- signals for the mm buses
signal
reg_diagnostics_front_mosi
:
t_mem_mosi_arr
;
signal
reg_diagnostics_front_miso
:
t_mem_miso_arr
;
signal
reg_hdr_insert_front_mosi
:
t_mem_mosi
;
signal
ram_hdr_insert_front_mosi
:
t_mem_mosi
;
signal
ram_hdr_remove_front_mosi
:
t_mem_mosi
;
signal
ram_hdr_remove_front_miso
:
t_mem_miso
;
signal
reg_mac_front_mosi
:
t_mem_mosi
;
signal
reg_mac_front_miso
:
t_mem_miso
;
signal
reg_diagnostics_back_mosi
:
t_mem_mosi_arr
;
signal
reg_diagnostics_back_miso
:
t_mem_miso_arr
;
signal
reg_hdr_insert_back_mosi
:
t_mem_mosi
;
signal
ram_hdr_insert_back_mosi
:
t_mem_mosi
;
signal
ram_hdr_remove_back_mosi
:
t_mem_mosi
;
signal
ram_hdr_remove_back_miso
:
t_mem_miso
;
signal
reg_mac_back_mosi
:
t_mem_mosi
;
signal
reg_mac_back_miso
:
t_mem_miso
;
-- signal xaui_rx_arr_dummy : t_unb_xaui_sl_2arr(47 downto 0) := (others=>"0000");
signal
xaui_rx_arr_dummy
:
t_xaui_arr
(
47
DOWNTO
0
);
-- signals for the transceivers
signal
tx_serial_data_front
:
std_logic_vector
(
47
downto
0
);
signal
rx_serial_data_front
:
std_logic_vector
(
47
downto
0
);
signal
dataloopback_front
:
std_logic_vector
(
3071
downto
0
);
signal
controlloopback_front
:
std_logic_vector
(
383
downto
0
);
signal
tx_serdesclk_front
:
std_logic_vector
(
47
downto
0
);
signal
validloopback_front
:
std_logic_vector
(
47
downto
0
);
signal
tx_analogreset_front
:
std_logic_vector
(
47
downto
0
);
signal
tx_digitalreset_front
:
std_logic_vector
(
47
downto
0
);
signal
rx_analogreset_front
:
std_logic_vector
(
47
downto
0
);
signal
rx_digitalreset_front
:
std_logic_vector
(
47
downto
0
);
signal
tx_cal_busy_front
:
std_logic_vector
(
47
downto
0
);
signal
rx_cal_busy_front
:
std_logic_vector
(
47
downto
0
);
signal
txpll_cal_busy_front
:
std_logic_vector
(
47
downto
0
);
signal
pll_cal_busy_front
:
std_logic
;
signal
rx_is_lockedtodata_front
:
std_logic_vector
(
47
downto
0
);
signal
pll_powerdown_front
:
std_logic_vector
(
0
downto
0
);
signal
pll_locked_front
:
std_logic_vector
(
0
downto
0
);
signal
tx_serial_clk_front
:
std_logic_vector
(
47
downto
0
);
signal
mcgb_serial_clk_front
:
std_logic
;
signal
diagnostics_front_snk_in_arr
:
t_dp_sosi_arr
(
47
DOWNTO
0
);
signal
diagnostics_front_snk_out_arr
:
t_dp_siso_arr
(
47
DOWNTO
0
);
signal
diagnostics_front_src_out_arr
:
t_dp_sosi_arr
(
47
DOWNTO
0
);
signal
diagnostics_front_src_in_arr
:
t_dp_siso_arr
(
47
DOWNTO
0
);
signal
tx_serial_data_back
:
std_logic_vector
(
47
downto
0
);
signal
rx_serial_data_back
:
std_logic_vector
(
47
downto
0
);
signal
dataloopback_back
:
std_logic_vector
(
3071
downto
0
);
signal
controlloopback_back
:
std_logic_vector
(
383
downto
0
);
signal
tx_serdesclk_back
:
std_logic_vector
(
47
downto
0
);
signal
validloopback_back
:
std_logic_vector
(
47
downto
0
);
signal
tx_analogreset_back
:
std_logic_vector
(
47
downto
0
);
signal
tx_digitalreset_back
:
std_logic_vector
(
47
downto
0
);
signal
rx_analogreset_back
:
std_logic_vector
(
47
downto
0
);
signal
rx_digitalreset_back
:
std_logic_vector
(
47
downto
0
);
signal
tx_cal_busy_back
:
std_logic_vector
(
47
downto
0
);
signal
rx_cal_busy_back
:
std_logic_vector
(
47
downto
0
);
signal
txpll_cal_busy_back
:
std_logic_vector
(
47
downto
0
);
signal
pll_cal_busy_back_upper
:
std_logic
;
signal
pll_cal_busy_back_lower
:
std_logic
;
signal
rx_is_lockedtodata_back
:
std_logic_vector
(
47
downto
0
);
signal
pll_powerdown_back_upper
:
std_logic_vector
(
0
downto
0
);
signal
pll_powerdown_back_lower
:
std_logic_vector
(
0
downto
0
);
signal
pll_locked_back_upper
:
std_logic_vector
(
0
downto
0
);
signal
pll_locked_back_lower
:
std_logic_vector
(
0
downto
0
);
signal
tx_serial_clk_back
:
std_logic_vector
(
47
downto
0
);
signal
mcgb_serial_clk_back_upper
:
std_logic
;
signal
mcgb_serial_clk_back_lower
:
std_logic
;
signal
diagnostics_back_snk_in_arr
:
t_dp_sosi_arr
(
47
DOWNTO
0
);
signal
diagnostics_back_snk_out_arr
:
t_dp_siso_arr
(
47
DOWNTO
0
);
signal
diagnostics_back_src_out_arr
:
t_dp_sosi_arr
(
47
DOWNTO
0
);
signal
diagnostics_back_src_in_arr
:
t_dp_siso_arr
(
47
DOWNTO
0
);
-- signals for the bidirectional and misc ios
signal
inta_in
:
std_logic
;
...
...
@@ -560,7 +500,7 @@ begin
);
-- -- ****** Front side transceivers ******
-- -- ****** Front side transceivers
and diagnostics
******
--
RING_0_TX
<=
tx_serial_data_front
(
47
downto
36
);
QSFP_0_TX
<=
tx_serial_data_front
(
35
downto
32
);
...
...
@@ -575,203 +515,141 @@ begin
&
QSFP_0_RX
&
QSFP_1_RX
&
QSFP_2_RX
&
QSFP_3_RX
&
QSFP_4_RX
&
QSFP_5_RX
&
RING_1_RX
;
transceiver_phy_front
:
transceiver_phy
port
map
(
tx_analogreset
=>
tx_analogreset_front
,
tx_digitalreset
=>
tx_digitalreset_front
,
rx_analogreset
=>
rx_analogreset_front
,
rx_digitalreset
=>
rx_digitalreset_front
,
tx_cal_busy
=>
tx_cal_busy_front
,
rx_cal_busy
=>
rx_cal_busy_front
,
rx_is_lockedtodata
=>
rx_is_lockedtodata_front
,
tx_serial_clk0
=>
tx_serial_clk_front
,
rx_cdr_refclk0
=>
sa_clk
,
gen_diagnostics_front
:
for
i
in
0
to
2
generate
mms_diagnostics_front
:
ENTITY
diagnostics_lib
.
mms_diagnostics
GENERIC
MAP
(
g_data_w
=>
c_xgmii_data_w
,
g_block_len
=>
c_block_len
,
g_nof_streams
=>
16
,
g_separate_clk
=>
FALSE
)
PORT
MAP
(
mm_rst
=>
reset_p
,
mm_clk
=>
mm_clk
,
st_rst
=>
reset_p
,
st_clk
=>
mm_clk
,
mm_mosi
=>
reg_diagnostics_front_mosi
(
i
),
mm_miso
=>
reg_diagnostics_front_miso
(
i
),
src_out_arr
=>
diagnostics_front_src_out_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
src_in_arr
=>
diagnostics_front_src_in_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
snk_out_arr
=>
diagnostics_front_snk_out_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
snk_in_arr
=>
diagnostics_front_snk_in_arr
((
i
+
1
)
*
16-1
downto
i
*
16
)
);
end
generate
gen_diagnostics_front
;
tr_10GbE_front
:
ENTITY
tr_10GbE_lib
.
tr_10GbE
GENERIC
MAP
(
g_technology
=>
c_tech_arria10
,
g_sim
=>
false
,
g_sim_level
=>
0
,
g_nof_macs
=>
48
,
g_use_mdio
=>
false
,
g_mdio_epcs_dis
=>
false
,
g_lpbk_sosi
=>
false
,
g_lpbk_xgmii
=>
false
,
g_lpbk_xaui
=>
false
,
g_use_hdr_ram
=>
true
)
PORT
MAP
(
-- System
mm_rst
=>
reset_p
,
mm_clk
=>
mm_clk
,
tr_clk
=>
SA_CLK
,
cal_rec_clk
=>
mm_clk
,
dp_rst
=>
reset_p
,
dp_clk
=>
mm_clk
,
-- MM registers
reg_mac_mosi
=>
reg_mac_front_mosi
,
reg_mac_miso
=>
reg_mac_front_miso
,
reg_hdr_insert_mosi
=>
reg_hdr_insert_front_mosi
,
ram_hdr_insert_mosi
=>
ram_hdr_insert_front_mosi
,
ram_hdr_remove_mosi
=>
ram_hdr_remove_front_mosi
,
ram_hdr_remove_miso
=>
ram_hdr_remove_front_miso
,
src_out_arr
=>
diagnostics_front_snk_in_arr
,
src_in_arr
=>
diagnostics_front_snk_out_arr
,
snk_out_arr
=>
diagnostics_front_src_in_arr
,
snk_in_arr
=>
diagnostics_front_src_out_arr
,
xaui_tx_out_arr
=>
open
,
xaui_rx_in_arr
=>
xaui_rx_arr_dummy
,
tx_serial_data
=>
tx_serial_data_front
,
rx_serial_data
=>
rx_serial_data_front
,
tx_coreclkin
=>
tx_serdesclk_front
,
-- write side clock for tx fifo
rx_coreclkin
=>
tx_serdesclk_front
,
tx_clkout
=>
tx_serdesclk_front
,
rx_clkout
=>
open
,
tx_enh_data_valid
=>
validloopback_front
,
rx_enh_data_valid
=>
validloopback_front
,
rx_enh_blk_lock
=>
open
,
tx_parallel_data
=>
dataloopback_front
,
tx_control
=>
controlloopback_front
,
tx_err_ins
=>
(
others
=>
'0'
),
-- use to insert sync errors
unused_tx_parallel_data
=>
(
others
=>
'0'
),
unused_tx_control
=>
(
others
=>
'0'
),
rx_parallel_data
=>
dataloopback_front
,
rx_control
=>
controlloopback_front
,
unused_rx_parallel_data
=>
open
,
unused_rx_control
=>
open
mdio_mdc_arr
=>
open
,
mdio_mdat_in_arr
=>
(
others
=>
'0'
),
mdio_mdat_oen_arr
=>
open
);
transceiver_reset_front
:
transceiver_reset_controller
port
map
(
clock
=>
clk
,
reset
=>
reset_p
,
pll_powerdown
=>
pll_powerdown_front
,
tx_analogreset
=>
tx_analogreset_front
,
tx_digitalreset
=>
tx_digitalreset_front
,
tx_ready
=>
open
,
pll_locked
=>
pll_locked_front
,
pll_select
=>
"0"
,
tx_cal_busy
=>
txpll_cal_busy_front
,
rx_analogreset
=>
rx_analogreset_front
,
rx_digitalreset
=>
rx_digitalreset_front
,
rx_ready
=>
open
,
rx_is_lockedtodata
=>
rx_is_lockedtodata_front
,
rx_cal_busy
=>
rx_cal_busy_front
);
transceiver_pll_front
:
transceiver_pll
port
map
(
pll_powerdown
=>
pll_powerdown_front
(
0
),
pll_refclk0
=>
sa_clk
,
pll_locked
=>
pll_locked_front
(
0
),
pll_cal_busy
=>
pll_cal_busy_front
,
mcgb_rst
=>
pll_powerdown_front
(
0
),
mcgb_serial_clk
=>
mcgb_serial_clk_front
);
tx_serial_clk_front
<=
(
others
=>
mcgb_serial_clk_front
);
txpll_cal_busy_front
<=
tx_cal_busy_front
when
pll_cal_busy_front
=
'0'
else
(
others
=>
'1'
);
-- ****** Back side transceivers ******
-- upper 24 transceivers use sb_clk
BCK_TX
<=
tx_serial_data_back
(
47
downto
0
);
rx_serial_data_back
<=
BCK_RX
;
transceiver_phy_back_upper
:
transceiver_phy_24channel
port
map
(
tx_analogreset
=>
tx_analogreset_back
(
47
downto
24
),
tx_digitalreset
=>
tx_digitalreset_back
(
47
downto
24
),
rx_analogreset
=>
rx_analogreset_back
(
47
downto
24
),
rx_digitalreset
=>
rx_digitalreset_back
(
47
downto
24
),
tx_cal_busy
=>
tx_cal_busy_back
(
47
downto
24
),
rx_cal_busy
=>
rx_cal_busy_back
(
47
downto
24
),
rx_is_lockedtodata
=>
rx_is_lockedtodata_back
(
47
downto
24
),
tx_serial_clk0
=>
tx_serial_clk_back
(
47
downto
24
),
rx_cdr_refclk0
=>
sb_clk
,
tx_serial_data
=>
tx_serial_data_back
(
47
downto
24
),
rx_serial_data
=>
rx_serial_data_back
(
47
downto
24
),
tx_coreclkin
=>
tx_serdesclk_back
(
47
downto
24
),
-- write side clock for tx fifo
rx_coreclkin
=>
tx_serdesclk_back
(
47
downto
24
),
tx_clkout
=>
tx_serdesclk_back
(
47
downto
24
),
rx_clkout
=>
open
,
tx_enh_data_valid
=>
validloopback_back
(
47
downto
24
),
rx_enh_data_valid
=>
validloopback_back
(
47
downto
24
),
rx_enh_blk_lock
=>
open
,
tx_parallel_data
=>
dataloopback_back
(
3071
downto
1536
),
tx_control
=>
controlloopback_back
(
383
downto
192
),
tx_err_ins
=>
(
others
=>
'0'
),
-- use to insert sync errors
unused_tx_parallel_data
=>
(
others
=>
'0'
),
unused_tx_control
=>
(
others
=>
'0'
),
rx_parallel_data
=>
dataloopback_back
(
3071
downto
1536
),
rx_control
=>
controlloopback_back
(
383
downto
192
),
unused_rx_parallel_data
=>
open
,
unused_rx_control
=>
open
);
transceiver_reset_back_upper
:
transceiver_reset_controller_24
port
map
(
clock
=>
clk
,
reset
=>
reset_p
,
pll_powerdown
=>
pll_powerdown_back_upper
,
tx_analogreset
=>
tx_analogreset_back
(
47
downto
24
),
tx_digitalreset
=>
tx_digitalreset_back
(
47
downto
24
),
tx_ready
=>
open
,
pll_locked
=>
pll_locked_back_upper
,
pll_select
=>
"0"
,
tx_cal_busy
=>
txpll_cal_busy_back
(
47
downto
24
),
rx_analogreset
=>
rx_analogreset_back
(
47
downto
24
),
rx_digitalreset
=>
rx_digitalreset_back
(
47
downto
24
),
rx_ready
=>
open
,
rx_is_lockedtodata
=>
rx_is_lockedtodata_back
(
47
downto
24
),
rx_cal_busy
=>
rx_cal_busy_back
(
47
downto
24
)
);
transceiver_pll_back_upper
:
transceiver_pll
port
map
(
pll_powerdown
=>
pll_powerdown_back_upper
(
0
),
pll_refclk0
=>
sb_clk
,
pll_locked
=>
pll_locked_back_upper
(
0
),
pll_cal_busy
=>
pll_cal_busy_back_upper
,
mcgb_rst
=>
pll_powerdown_back_upper
(
0
),
mcgb_serial_clk
=>
mcgb_serial_clk_back_upper
);
tx_serial_clk_back
(
47
downto
24
)
<=
(
others
=>
mcgb_serial_clk_back_upper
);
txpll_cal_busy_back
(
47
downto
24
)
<=
tx_cal_busy_back
(
47
downto
24
)
when
pll_cal_busy_back_upper
=
'0'
else
(
others
=>
'1'
);
-- lower 24 transceivers use sb_clk
transceiver_phy_back_lower
:
transceiver_phy_24channel
port
map
(
tx_analogreset
=>
tx_analogreset_back
(
23
downto
0
),
tx_digitalreset
=>
tx_digitalreset_back
(
23
downto
0
),
rx_analogreset
=>
rx_analogreset_back
(
23
downto
0
),
rx_digitalreset
=>
rx_digitalreset_back
(
23
downto
0
),
tx_cal_busy
=>
tx_cal_busy_back
(
23
downto
0
),
rx_cal_busy
=>
rx_cal_busy_back
(
23
downto
0
),
rx_is_lockedtodata
=>
rx_is_lockedtodata_back
(
23
downto
0
),
tx_serial_clk0
=>
tx_serial_clk_back
(
23
downto
0
),
rx_cdr_refclk0
=>
bck_ref_clk
,
tx_serial_data
=>
tx_serial_data_back
(
23
downto
0
),
rx_serial_data
=>
rx_serial_data_back
(
23
downto
0
),
tx_coreclkin
=>
tx_serdesclk_back
(
23
downto
0
),
-- write side clock for tx fifo
rx_coreclkin
=>
tx_serdesclk_back
(
23
downto
0
),
tx_clkout
=>
tx_serdesclk_back
(
23
downto
0
),
rx_clkout
=>
open
,
tx_enh_data_valid
=>
validloopback_back
(
23
downto
0
),
rx_enh_data_valid
=>
validloopback_back
(
23
downto
0
),
rx_enh_blk_lock
=>
open
,
tx_parallel_data
=>
dataloopback_back
(
1535
downto
0
),
tx_control
=>
controlloopback_back
(
191
downto
0
),
tx_err_ins
=>
(
others
=>
'0'
),
-- use to insert sync errors
unused_tx_parallel_data
=>
(
others
=>
'0'
),
unused_tx_control
=>
(
others
=>
'0'
),
rx_parallel_data
=>
dataloopback_back
(
1535
downto
0
),
rx_control
=>
controlloopback_back
(
191
downto
0
),
unused_rx_parallel_data
=>
open
,
unused_rx_control
=>
open
gen_diagnostics_back
:
for
i
in
0
to
2
generate
mms_diagnostics_back
:
ENTITY
diagnostics_lib
.
mms_diagnostics
GENERIC
MAP
(
g_data_w
=>
c_xgmii_data_w
,
g_block_len
=>
c_block_len
,
g_nof_streams
=>
16
,
g_separate_clk
=>
FALSE
)
PORT
MAP
(
mm_rst
=>
reset_p
,
mm_clk
=>
mm_clk
,
st_rst
=>
reset_p
,
st_clk
=>
mm_clk
,
mm_mosi
=>
reg_diagnostics_back_mosi
(
i
),
mm_miso
=>
reg_diagnostics_back_miso
(
i
),
src_out_arr
=>
diagnostics_back_src_out_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
src_in_arr
=>
diagnostics_back_src_in_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
snk_out_arr
=>
diagnostics_back_snk_out_arr
((
i
+
1
)
*
16-1
downto
i
*
16
),
snk_in_arr
=>
diagnostics_back_snk_in_arr
((
i
+
1
)
*
16-1
downto
i
*
16
)
);
transceiver_reset_back_lower
:
transceiver_reset_controller_24
port
map
(
clock
=>
clk
,
reset
=>
reset_p
,
pll_powerdown
=>
pll_powerdown_back_lower
,
tx_analogreset
=>
tx_analogreset_back
(
23
downto
0
),
tx_digitalreset
=>
tx_digitalreset_back
(
23
downto
0
),
tx_ready
=>
open
,
pll_locked
=>
pll_locked_back_lower
,
pll_select
=>
"0"
,
tx_cal_busy
=>
txpll_cal_busy_back
(
23
downto
0
),
rx_analogreset
=>
rx_analogreset_back
(
23
downto
0
),
rx_digitalreset
=>
rx_digitalreset_back
(
23
downto
0
),
rx_ready
=>
open
,
rx_is_lockedtodata
=>
rx_is_lockedtodata_back
(
23
downto
0
),
rx_cal_busy
=>
rx_cal_busy_back
(
23
downto
0
)
end
generate
gen_diagnostics_back
;
tr_10GbE_back
:
ENTITY
tr_10GbE_lib
.
tr_10GbE
GENERIC
MAP
(
g_technology
=>
c_tech_arria10
,
g_sim
=>
false
,
g_sim_level
=>
0
,
g_nof_macs
=>
48
,
g_use_mdio
=>
false
,
g_mdio_epcs_dis
=>
false
,
g_lpbk_sosi
=>
false
,
g_lpbk_xgmii
=>
false
,
g_lpbk_xaui
=>
false
,
g_use_hdr_ram
=>
true
)
PORT
MAP
(
-- System
mm_rst
=>
reset_p
,
mm_clk
=>
mm_clk
,
tr_clk
=>
SA_CLK
,
cal_rec_clk
=>
mm_clk
,
dp_rst
=>
reset_p
,
dp_clk
=>
mm_clk
,
-- MM registers
reg_mac_mosi
=>
reg_mac_back_mosi
,
reg_mac_miso
=>
reg_mac_back_miso
,
reg_hdr_insert_mosi
=>
reg_hdr_insert_back_mosi
,
ram_hdr_insert_mosi
=>
ram_hdr_insert_back_mosi
,
ram_hdr_remove_mosi
=>
ram_hdr_remove_back_mosi
,
ram_hdr_remove_miso
=>
ram_hdr_remove_back_miso
,
src_out_arr
=>
diagnostics_back_snk_in_arr
,
src_in_arr
=>
diagnostics_back_snk_out_arr
,
snk_out_arr
=>
diagnostics_back_src_in_arr
,
snk_in_arr
=>
diagnostics_back_src_out_arr
,
xaui_tx_out_arr
=>
open
,
xaui_rx_in_arr
=>
xaui_rx_arr_dummy
,
tx_serial_data
=>
tx_serial_data_back
,
rx_serial_data
=>
rx_serial_data_back
,
mdio_mdc_arr
=>
open
,
mdio_mdat_in_arr
=>
(
others
=>
'0'
),
mdio_mdat_oen_arr
=>
open
);
transceiver_pll_back_lower
:
transceiver_pll
port
map
(
pll_powerdown
=>
pll_powerdown_back_lower
(
0
),
pll_refclk0
=>
bck_ref_clk
,
pll_locked
=>
pll_locked_back_lower
(
0
),
pll_cal_busy
=>
pll_cal_busy_back_lower
,
mcgb_rst
=>
pll_powerdown_back_lower
(
0
),
mcgb_serial_clk
=>
mcgb_serial_clk_back_lower
);
tx_serial_clk_back
(
23
downto
0
)
<=
(
others
=>
mcgb_serial_clk_back_lower
);
txpll_cal_busy_back
(
23
downto
0
)
<=
tx_cal_busy_back
(
23
downto
0
)
when
pll_cal_busy_back_lower
=
'0'
else
(
others
=>
'1'
);
-- ****** node control for resets and wdi
...
...
@@ -808,7 +686,7 @@ begin
-- ****** i2c interfaces ******
u_qsys
:
unb2_
pinning
_qsys
u_qsys
:
unb2_
test
_qsys
port
map
(
clk_clk
=>
mm_clk
,
reset_reset_n
=>
reset_n
,
...
...
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