Ported tse_sgmii_lvds v9.1 from $UNB to ip_stratix_tse_sgmii_lvds in $RADIOHDL.

de029b85 · Eric Kooistra · 0cdf162d · de029b85 · de029b85 · de029b85
Commit de029b85 authored Jun 11, 2014 by Eric Kooistra
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.qip
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.qip
+set_global_assignment -name IP_TOOL_NAME "Triple Speed Ethernet"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ip_stratixiv_tse_sgmii_lvds.vhd"]
+set_global_assignment -name SEARCH_PATH  [file join $::quartus(qip_path) "." ]
+set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) triple_speed_ethernet-library ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_align_sync.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_arriagx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_basic.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt4gxb_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altgx_civgx_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altshifttaps.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altsyncram_dpm_fifo.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_13.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_24.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_34.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_1246.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_14_44.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_36_10.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_bin_cnt.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_carrier_sense.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_clk_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_clk_gen.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_colision_detect.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc328checker.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc328generator.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc32ctl8.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc32galois8.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dc_fifo.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dec10b8b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dec_func.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dpram_16x32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dpram_8x32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_enc8b10b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_mac_rx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_mac_tx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_retransmit_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_geth_pcs_wo_ratematch.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gige_reset_ctrl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gmii_io.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gray_cnt.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gxb_gige_inst.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_hashing.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_host_control.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_host_control_small.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lb_read_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lb_wrt_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lfsr_10.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_loopback_ff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_control.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_gige_woff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_ena.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_strx_gx_ena.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_woff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_rx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_tx.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_woff.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_woff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_magic_detection.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_clk_gen.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_reg.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_rx_if.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_rx_if_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_tx_if.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_tx_if_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_channel_arbiter.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_control.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_host_control.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_pma.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_quad_16x32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_quad_8x32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_register_map.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_register_map_small.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_retransmit_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_in1.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_in4.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_module.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_out1.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_out4.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_converter.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_counter_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_encapsulation.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_encapsulation_strx_gx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl_32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl_32_shift16.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_length.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_fifo_rd.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_min_ff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_stat_extract.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_sync.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sdpm_altsyncram.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sdpm_gen.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_div.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_enable.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_scheduler.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_shared_mac_control.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_shared_register_map.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter8.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter_fifo32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter_fifo8.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x_strx_gx.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x_strx_gx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1geth.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_autoneg.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_fifoless_1geth.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_gen_host.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_gen_host.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_mdio.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac_pcs_gige.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_pcs.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_pcs_strx_gx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_rx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_rx_converter.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_sgmii.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_sgmii_strx_gx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_tx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_tx_converter.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_wo_fifo.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_wo_fifo_10_100_1000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_w_fifo.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_w_fifo_10_100_1000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_converter.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_counter_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_encapsulation.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl_32.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl_32_shift16.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_length.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_read_cntl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_min_ff.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_stat_extract.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.vhd ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.cmp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.bsf ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.vho ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.qip ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_lvds.html ]
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+-- megafunction wizard: %Triple Speed Ethernet v9.1%
+-- GENERATION: XML
+
+-- ============================================================
+-- Megafunction Name(s):
+-- 			altera_tse_mac_pcs_pma
+-- ============================================================
+-- Generated by Triple Speed Ethernet 9.1 [Altera, IP Toolbench 1.3.0 Build 304]
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- ************************************************************
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Any megafunction design, and related net list (encrypted or decrypted),
+-- support information, device programming or simulation file, and any other
+-- associated documentation or information provided by Altera or a partner
+-- under Altera's Megafunction Partnership Program may be used only to
+-- program PLD devices (but not masked PLD devices) from Altera.  Any other
+-- use of such megafunction design, net list, support information, device
+-- programming or simulation file, or any other related documentation or
+-- information is prohibited for any other purpose, including, but not
+-- limited to modification, reverse engineering, de-compiling, or use with
+-- any other silicon devices, unless such use is explicitly licensed under
+-- a separate agreement with Altera or a megafunction partner.  Title to
+-- the intellectual property, including patents, copyrights, trademarks,
+-- trade secrets, or maskworks, embodied in any such megafunction design,
+-- net list, support information, device programming or simulation file, or
+-- any other related documentation or information provided by Altera or a
+-- megafunction partner, remains with Altera, the megafunction partner, or
+-- their respective licensors.  No other licenses, including any licenses
+-- needed under any third party's intellectual property, are provided herein.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+ENTITY ip_stratixiv_tse_sgmii_lvds IS
+	PORT (
+		ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		ff_tx_eop	: IN STD_LOGIC;
+		ff_tx_err	: IN STD_LOGIC;
+		ff_tx_mod	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		ff_tx_sop	: IN STD_LOGIC;
+		ff_tx_wren	: IN STD_LOGIC;
+		ff_tx_clk	: IN STD_LOGIC;
+		ff_rx_rdy	: IN STD_LOGIC;
+		ff_rx_clk	: IN STD_LOGIC;
+		address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		read	: IN STD_LOGIC;
+		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		write	: IN STD_LOGIC;
+		clk	: IN STD_LOGIC;
+		reset	: IN STD_LOGIC;
+		rxp	: IN STD_LOGIC;
+		ref_clk	: IN STD_LOGIC;
+		ff_tx_crc_fwd	: IN STD_LOGIC;
+		ff_tx_rdy	: OUT STD_LOGIC;
+		ff_rx_data	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		ff_rx_dval	: OUT STD_LOGIC;
+		ff_rx_eop	: OUT STD_LOGIC;
+		ff_rx_mod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+		ff_rx_sop	: OUT STD_LOGIC;
+		rx_err	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		waitrequest	: OUT STD_LOGIC;
+		led_an	: OUT STD_LOGIC;
+		led_char_err	: OUT STD_LOGIC;
+		led_link	: OUT STD_LOGIC;
+		led_disp_err	: OUT STD_LOGIC;
+		txp	: OUT STD_LOGIC;
+		ff_tx_septy	: OUT STD_LOGIC;
+		tx_ff_uflow	: OUT STD_LOGIC;
+		ff_tx_a_full	: OUT STD_LOGIC;
+		ff_tx_a_empty	: OUT STD_LOGIC;
+		rx_err_stat	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
+		rx_frm_type	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		ff_rx_dsav	: OUT STD_LOGIC;
+		ff_rx_a_full	: OUT STD_LOGIC;
+		ff_rx_a_empty	: OUT STD_LOGIC
+	);
+END ip_stratixiv_tse_sgmii_lvds;
+
+ARCHITECTURE SYN OF ip_stratixiv_tse_sgmii_lvds IS
+
+
+	COMPONENT altera_tse_mac_pcs_pma
+	GENERIC (
+		ENABLE_MAGIC_DETECT	: NATURAL;
+		ENABLE_MDIO	: NATURAL;
+		ENABLE_SHIFT16	: NATURAL;
+		ENABLE_SUP_ADDR	: NATURAL;
+		CORE_VERSION	: STD_LOGIC_VECTOR := X"0901";
+		CRC32GENDELAY	: NATURAL;
+		MDIO_CLK_DIV	: NATURAL;
+		ENA_HASH	: NATURAL;
+		USE_SYNC_RESET	: NATURAL;
+		STAT_CNT_ENA	: NATURAL;
+		ENABLE_EXTENDED_STAT_REG	: NATURAL;
+		ENABLE_HD_LOGIC	: NATURAL;
+		REDUCED_INTERFACE_ENA	: NATURAL;
+		CRC32S1L2_EXTERN	: NATURAL;
+		ENABLE_GMII_LOOPBACK	: NATURAL;
+		CRC32DWIDTH	: NATURAL;
+		CUST_VERSION	: NATURAL;
+		RESET_LEVEL	: STD_LOGIC_VECTOR := X"01";
+		CRC32CHECK16BIT	: STD_LOGIC_VECTOR := X"00";
+		ENABLE_MAC_FLOW_CTRL	: NATURAL;
+		ENABLE_MAC_TXADDR_SET	: NATURAL;
+		ENABLE_MAC_RX_VLAN	: NATURAL;
+		ENABLE_MAC_TX_VLAN	: NATURAL;
+		SYNCHRONIZER_DEPTH	: NATURAL;
+		EG_FIFO	: NATURAL;
+		EG_ADDR	: NATURAL;
+		ING_FIFO	: NATURAL;
+		ENABLE_ENA	: NATURAL;
+		ING_ADDR	: NATURAL;
+		RAM_TYPE	: STRING;
+		INSERT_TA	: NATURAL;
+		ENABLE_MACLITE	: NATURAL;
+		MACLITE_GIGE	: NATURAL;
+		PHY_IDENTIFIER	: STD_LOGIC_VECTOR := X"00000000";
+		DEV_VERSION	: STD_LOGIC_VECTOR := X"0901";
+		ENABLE_SGMII	: NATURAL;
+		DEVICE_FAMILY	: STRING;
+		EXPORT_PWRDN	: NATURAL;
+		TRANSCEIVER_OPTION	: NATURAL;
+		ENABLE_ALT_RECONFIG	: NATURAL
+	);
+	PORT (
+		ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		ff_tx_eop	: IN STD_LOGIC;
+		ff_tx_err	: IN STD_LOGIC;
+		ff_tx_mod	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		ff_tx_sop	: IN STD_LOGIC;
+		ff_tx_wren	: IN STD_LOGIC;
+		ff_tx_clk	: IN STD_LOGIC;
+		ff_rx_rdy	: IN STD_LOGIC;
+		ff_rx_clk	: IN STD_LOGIC;
+		address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		read	: IN STD_LOGIC;
+		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		write	: IN STD_LOGIC;
+		clk	: IN STD_LOGIC;
+		reset	: IN STD_LOGIC;
+		rxp	: IN STD_LOGIC;
+		ref_clk	: IN STD_LOGIC;
+		ff_tx_crc_fwd	: IN STD_LOGIC;
+		ff_tx_rdy	: OUT STD_LOGIC;
+		ff_rx_data	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		ff_rx_dval	: OUT STD_LOGIC;
+		ff_rx_eop	: OUT STD_LOGIC;
+		ff_rx_mod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+		ff_rx_sop	: OUT STD_LOGIC;
+		rx_err	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		waitrequest	: OUT STD_LOGIC;
+		led_an	: OUT STD_LOGIC;
+		led_char_err	: OUT STD_LOGIC;
+		led_link	: OUT STD_LOGIC;
+		led_disp_err	: OUT STD_LOGIC;
+		txp	: OUT STD_LOGIC;
+		ff_tx_septy	: OUT STD_LOGIC;
+		tx_ff_uflow	: OUT STD_LOGIC;
+		ff_tx_a_full	: OUT STD_LOGIC;
+		ff_tx_a_empty	: OUT STD_LOGIC;
+		rx_err_stat	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
+		rx_frm_type	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		ff_rx_dsav	: OUT STD_LOGIC;
+		ff_rx_a_full	: OUT STD_LOGIC;
+		ff_rx_a_empty	: OUT STD_LOGIC
+	);
+
+	END COMPONENT;
+
+BEGIN
+
+	altera_tse_mac_pcs_pma_inst : altera_tse_mac_pcs_pma
+	GENERIC MAP (
+		ENABLE_MAGIC_DETECT => 0,
+		ENABLE_MDIO => 0,
+		ENABLE_SHIFT16 => 1,
+		ENABLE_SUP_ADDR => 0,
+		CORE_VERSION => X"0901",
+		CRC32GENDELAY => 6,
+		MDIO_CLK_DIV => 40,
+		ENA_HASH => 0,
+		USE_SYNC_RESET => 0,
+		STAT_CNT_ENA => 0,
+		ENABLE_EXTENDED_STAT_REG => 0,
+		ENABLE_HD_LOGIC => 0,
+		REDUCED_INTERFACE_ENA => 0,
+		CRC32S1L2_EXTERN => 0,
+		ENABLE_GMII_LOOPBACK => 1,
+		CRC32DWIDTH => 8,
+		CUST_VERSION => 0,
+		RESET_LEVEL => X"01",
+		CRC32CHECK16BIT => X"00",
+		ENABLE_MAC_FLOW_CTRL => 0,
+		ENABLE_MAC_TXADDR_SET => 1,
+		ENABLE_MAC_RX_VLAN => 0,
+		ENABLE_MAC_TX_VLAN => 0,
+		SYNCHRONIZER_DEPTH => 4,
+		EG_FIFO => 256,
+		EG_ADDR => 8,
+		ING_FIFO => 256,
+		ENABLE_ENA => 32,
+		ING_ADDR => 8,
+		RAM_TYPE => "M9K",
+		INSERT_TA => 0,
+		ENABLE_MACLITE => 0,
+		MACLITE_GIGE => 0,
+		PHY_IDENTIFIER => X"00000000",
+		DEV_VERSION => X"0901",
+		ENABLE_SGMII => 0,
+		DEVICE_FAMILY => "STRATIXIV",
+		EXPORT_PWRDN => 0,
+		TRANSCEIVER_OPTION => 1,
+		ENABLE_ALT_RECONFIG => 0
+	)
+	PORT MAP (
+		ff_tx_data  =>  ff_tx_data,
+		ff_tx_eop  =>  ff_tx_eop,
+		ff_tx_err  =>  ff_tx_err,
+		ff_tx_mod  =>  ff_tx_mod,
+		ff_tx_rdy  =>  ff_tx_rdy,
+		ff_tx_sop  =>  ff_tx_sop,
+		ff_tx_wren  =>  ff_tx_wren,
+		ff_tx_clk  =>  ff_tx_clk,
+		ff_rx_data  =>  ff_rx_data,
+		ff_rx_dval  =>  ff_rx_dval,
+		ff_rx_eop  =>  ff_rx_eop,
+		ff_rx_mod  =>  ff_rx_mod,
+		ff_rx_rdy  =>  ff_rx_rdy,
+		ff_rx_sop  =>  ff_rx_sop,
+		rx_err  =>  rx_err,
+		ff_rx_clk  =>  ff_rx_clk,
+		address  =>  address,
+		readdata  =>  readdata,
+		read  =>  read,
+		writedata  =>  writedata,
+		write  =>  write,
+		waitrequest  =>  waitrequest,
+		clk  =>  clk,
+		reset  =>  reset,
+		led_an  =>  led_an,
+		led_char_err  =>  led_char_err,
+		led_link  =>  led_link,
+		led_disp_err  =>  led_disp_err,
+		txp  =>  txp,
+		rxp  =>  rxp,
+		ref_clk  =>  ref_clk,
+		ff_tx_crc_fwd  =>  ff_tx_crc_fwd,
+		ff_tx_septy  =>  ff_tx_septy,
+		tx_ff_uflow  =>  tx_ff_uflow,
+		ff_tx_a_full  =>  ff_tx_a_full,
+		ff_tx_a_empty  =>  ff_tx_a_empty,
+		rx_err_stat  =>  rx_err_stat,
+		rx_frm_type  =>  rx_frm_type,
+		ff_rx_dsav  =>  ff_rx_dsav,
+		ff_rx_a_full  =>  ff_rx_a_full,
+		ff_rx_a_empty  =>  ff_rx_a_empty
+	);
+
+
+END SYN;
+
+
+-- =========================================================
+-- Triple Speed Ethernet Wizard Data
+-- ===============================
+-- DO NOT EDIT FOLLOWING DATA
+-- @Altera, IP Toolbench@
+-- Warning: If you modify this section, Triple Speed Ethernet Wizard may not be able to reproduce your chosen configuration.
+-- 
+-- Retrieval info: <?xml version="1.0"?>
+-- Retrieval info: <MEGACORE title="Triple Speed Ethernet MegaCore Function"  version="9.1"  build="304"  iptb_version="1.3.0 Build 304"  format_version="120" >
+-- Retrieval info:  <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.TSEMVCModel"  active_core="altera_tse_mac_pcs_pma" >
+-- Retrieval info:   <STATIC_SECTION>
+-- Retrieval info:    <PRIVATES>
+-- Retrieval info:     <NAMESPACE name = "parameterization">
+-- Retrieval info:      <PRIVATE name = "atlanticSinkClockRate" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "atlanticSinkClockSource" value="unassigned"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "atlanticSourceClockRate" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "atlanticSourceClockSource" value="unassigned"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "avalonSlaveClockRate" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "avalonSlaveClockSource" value="unassigned"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "avalonStNeighbours" value="{}"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "channel_count" value="1"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "core_variation" value="MAC_PCS"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "core_version" value="2305"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "crc32dwidth" value="8"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "crc32gendelay" value="6"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "crc32s1l2_extern" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "cust_version" value="0"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "dataBitsPerSymbol" value="8"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "dev_version" value="2305"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "deviceFamily" value="STRATIXIV"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "eg_addr" value="8"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "eg_fifo" value="256"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ena_hash" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_alt_reconfig" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_clk_sharing" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_ena" value="32"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_fifoless" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_gmii_loopback" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_hd_logic" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_mac_flow_ctrl" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_mac_txaddr_set" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_mac_vlan" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_maclite" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_magic_detect" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_multi_channel" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_pkt_class" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_pma" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_reg_sharing" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_sgmii" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_shift16" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_sup_addr" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enable_use_internal_fifo" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "export_calblkclk" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "export_pwrdn" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ext_stat_cnt_ena" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "gigeAdvanceMode" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ifGMII" value="MII_GMII"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ifPCSuseEmbeddedSerdes" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ing_addr" value="8"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ing_fifo" value="256"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "insert_ta" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "maclite_gige" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "max_channels" value="1"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "mdio_clk_div" value="40"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "phy_identifier" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "ramType" value="M9K"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "sopcSystemTopLevelName" value="system"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "stat_cnt_ena" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "timingAdapterName" value="timingAdapter"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "toolContext" value="STANDALONE"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "transceiver_type" value="LVDS_IO"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiEgFIFOSize" value="256 x 32 Bits"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiHostClockFrequency" value="0"  type="INTEGER"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiIngFIFOSize" value="256 x 32 Bits"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiMACFIFO" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiMACOptions" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiMDIOFreq" value="0.0 MHz"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiMIIInterfaceOptions" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiPCSInterface" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "uiPCSInterfaceOptions" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "useLvds" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "useMAC" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "useMDIO" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "usePCS" value="1"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "use_sync_reset" value="0"  type="BOOLEAN"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "simgen_enable">
+-- Retrieval info:      <PRIVATE name = "language" value="VHDL"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "enabled" value="1"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "gb_enabled" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "testbench">
+-- Retrieval info:      <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "project_name" value="system"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "tool_context" value="STANDALONE"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "constraint_file_generator">
+-- Retrieval info:      <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "instance_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "modelsim_script_generator">
+-- Retrieval info:      <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "instance_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "plugin_worker" value="1"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "europa_executor">
+-- Retrieval info:      <PRIVATE name = "plugin_worker" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "simgen">
+-- Retrieval info:      <PRIVATE name = "use_alt_top" value="0"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "filename" value="ip_stratixiv_tse_sgmii_lvds.vho"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "modelsim_wave_script_plugin">
+-- Retrieval info:      <PRIVATE name = "plugin_worker" value="1"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "nativelink">
+-- Retrieval info:      <PRIVATE name = "plugin_worker" value="1"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "language" value="VHDL"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "top_level_name" value="ip_stratixiv_tse_sgmii_lvds"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "greybox">
+-- Retrieval info:      <PRIVATE name = "filename" value="ip_stratixiv_tse_sgmii_lvds_syn.v"  type="STRING"  enable="1" />
+-- Retrieval info:     </NAMESPACE>
+-- Retrieval info:     <NAMESPACE name = "serializer"/>
+-- Retrieval info:    </PRIVATES>
+-- Retrieval info:    <FILES/>
+-- Retrieval info:    <PORTS/>
+-- Retrieval info:    <LIBRARIES/>
+-- Retrieval info:   </STATIC_SECTION>
+-- Retrieval info:  </NETLIST_SECTION>
+-- Retrieval info: </MEGACORE>
+-- =========================================================
+-- RELATED_FILES: ip_stratixiv_tse_sgmii_lvds.vhd, altera_tse_mac_pcs_pma.v;
+-- IPFS_FILES: ip_stratixiv_tse_sgmii_lvds.vho;
+-- =========================================================
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vho
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vho
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds_constraints.sdc
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds_constraints.sdc
+#####################################################################################
+# Copyright (C) 1991-2009 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+#####################################################################################
+
+#####################################################################################
+# Altera Triple-Speed Ethernet Megacore SDC file for use with the Quartus II 
+# TimeQuest Timing Analyzer
+#
+# To add this SDC file to your Quartus II project execute the following TCL
+# command in the Quartus II TCL console:
+# set_global_assignment -name SDC_FILE "ip_stratixiv_tse_sgmii_lvds"_constraints.sdc
+#
+# Generated on Wed Jun 16 16:45:06 CEST 2010
+#
+#####################################################################################
+# *************************************************************
+# Customer modifiable constraints, value is set default by constraints
+# *************************************************************
+set SYSTEM_PATH_PREFIX ""
+set TSE_CLOCK_FREQUENCY "125 MHz"
+set FIFO_CLOCK_FREQUENCY "100 MHz"
+set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz"    
+
+# name the clocks that will be coming into the tse core named changed from top level   
+set  TX_CLK             "tx_clk"                        
+set  RX_CLK             "rx_clk"                        
+set  CLK                "clk"
+set  FF_TX_CLK          "ff_tx_clk"
+set  FF_RX_CLK          "ff_rx_clk"
+set  TBI_TX_CLK         "tbi_tx_clk"
+set  TBI_RX_CLK         "tbi_rx_clk"
+set  REF_CLK            "ref_clk"
+        
+# General Option
+set IS_SOPC 0
+set VARIATION_NAME "ip_stratixiv_tse_sgmii_lvds"
+set DEVICE_FAMILY "STRATIXIV"
+
+# MAC Option
+set IS_MAC 1
+set NUMBER_OF_CHANNEL 1
+set IS_SMALLMAC 0
+set IS_SMALLMAC_GIGE 0
+set IS_FIFOLESS 0
+set IS_HALFDUPLEX 0
+set MII_INTERFACE "MII_GMII"
+
+# PCS Option
+set IS_PCS 1
+set IS_SGMII 0
+
+# PMA Option
+set IS_PMA 1
+set TRANSCEIVER_TYPE 1
+
+# GXB Option
+set IS_POWERDOWN 0
+
+# ********************** Please do not modify anything beyond this line ****************************
+# *********** The script might not work correctly if the following lines are modified **************
+
+   
+if { [ expr ($TRANSCEIVER_TYPE == 0)]} {
+	set CLOCK_1  "U_RXCLK"
+	set CLOCK_2 "U_TXCLK"
+} else {
+	set CLOCK_1 "U_RXCLK"
+	set CLOCK_2 "U_TXCLK"
+}
+
+if { [ expr ($IS_SOPC == 1) ]} {
+   set FROM_THE_VARIATION_NAME "_from_the_$VARIATION_NAME"
+   set TO_THE_VARIATION_NAME "_to_the_$VARIATION_NAME"
+} else {
+   set FROM_THE_VARIATION_NAME ""
+   set TO_THE_VARIATION_NAME ""
+}
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+# Uncommenting one of the following derive_pll_clocks lines
+# will instruct the TimeQuest Timing Analyzer to automatically
+# create derived clocks for all PLL outputs for all PLLs in a
+# Quartus design.
+# If the PLL inputs are constrained elsewhere, uncomment the
+# next line to automatically constrain all PLL output clocks.
+# derive_pll_clocks
+# If the PLL inputs are not constrained elsewhere, uncomment
+# the next line to automatically constrain all PLL input and
+# output clocks.
+# derive_pll_clocks -create_base_clocks
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+#Constrain timing for half duplex logic
+#  - Direct path as we are confirmed of this path
+if { [ expr ( $IS_FIFOLESS == 0 )] } {
+
+#  mac
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0)] } {
+      #Constrain MAC control interface clock
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
+
+      #Constrain MAC FIFO data interface clocks
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
+
+      #Constrain MAC network-side interface clocks
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TX_CLK]
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $RX_CLK]
+   }
+
+   #  macPcs
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
+      #Constrain MAC PCS control interface clock
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
+
+      #Constrain MAC PCS FIFO data interface clocks
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
+
+      #Constrain MAC PCS network-side interface clocks 
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
+   }
+
+   #  macPcsPma
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
+
+      #Constrain transceiver reference clock
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports  $REF_CLK]
+
+      #Constrain MAC PCS control interface clock
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports  $CLK]
+
+      #Constrain MAC PCS FIFO data interface clocks
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
+      create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
+   }
+
+   #  pcs
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
+
+	  #Cut the timing path betweeen unrelated clock domains
+	  
+   }
+
+   #  pcsPma
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
+      #Constrain PCS control interface clock
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports clk]
+
+      #Constrain transceiver reference clock
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports  $REF_CLK]
+   }
+
+   #  macPcsSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
+   }
+
+   # macPcsNoSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
+
+   }
+
+   #  macPcsPmaSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
+   }
+
+   #  macPcsPmaNoSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0)] } {
+   }
+
+   #  pmaAlt4Gxb
+   if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
+   }
+
+   #  pcsSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
+      #Constrain PCS GMII/MII interface clocks 
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
+    }
+
+   #  pcsNoSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
+      #Constrain PCS control interface clock
+      create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
+
+      #Constrain PCS network-side interface clocks
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
+      create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
+	  
+   }
+
+   #  pcsPmaSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
+      #Constrain PCS GMII/MII interface clocks 
+   } 
+   
+   derive_pll_clocks
+
+   #  pcsPmaNoSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
+   }
+
+   #  macPcsPmaLvdsSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
+     #Cut the timing path betweeen unrelated clock domains
+   }
+
+   #  macPcsPmaLvdsNoSgmii
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
+   }
+
+   #  macPcsPmaTransceiverSgmii=
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
+      #Cut the timing path betweeen unrelated clock domains
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
+   }
+
+   #  macPcsPmaTransceiverNoSgmii=
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
+      #Cut the timing path betweeen unrelated clock domains
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
+   }
+
+   #  pcsPmaLvdsSgmii=
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
+      #Cut the timing path betweeen unrelated clock domains
+   }
+
+   #  pcsPmaLvdsNoSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
+   }
+
+   #  pcsPmaTransceiverSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"])) ] } {
+      #Cut the timing path betweeen unrelated clock domains
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TSE_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group  [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
+   }
+
+   #  pcsPmaTransceiverNoSgmii
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
+      #Cut the timing path betweeen unrelated clock domains
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
+      set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
+   }
+
+   # Universal Clock Group setter
+  
+   set clocks_list [get_clocks *]
+
+   foreach_in_collection clock $clocks_list {
+   	set name [get_clock_info -name $clock]
+    		if {[ expr [regexp "altera_tse" $name] == 1]} {
+        		set_clock_groups -exclusive -group [get_clocks $name]
+    		   }
+	}
+
+
+} else {
+
+#  multiChannelFifoless
+
+
+#**************************************************************
+# Set Parameter
+#**************************************************************
+#**************************************************************
+
+#**************************************************************
+# Time Information
+#**************************************************************
+# Uncommenting one of the following derive_pll_clocks lines
+# will instruct the TimeQuest Timing Analyzer to automatically
+# create derived clocks for all PLL outputs for all PLLs in a
+# Quartus design.
+# If the PLL inputs are constrained elsewhere, uncomment the
+# next line to automatically constrain all PLL output clocks.
+
+# derive_pll_clocks
+
+# If the PLL inputs are not constrained elsewhere, uncomment
+# the next line to automatically constrain all PLL input and
+# output clocks.
+
+# derive_pll_clocks -create_base_clocks
+
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+#**************************************************************
+
+#All clocks used by TSE is named with prefix "altera_tse"
+#Constrain MAC PCS control interface clock
+
+if { [ expr $IS_SOPC == 0 ] } {
+	create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_sys_clk [ get_ports "$CLK"]
+}
+
+if { [ expr ($IS_FIFOLESS == 1) ] } {
+   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+   		if { [ expr ($IS_SOPC == 0) ] } {
+			create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_tx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
+			create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_rx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
+		} else {
+			create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_rx_clk_${x}_out" ]
+			create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_tx_clk_${x}_out" ]
+		}
+   }
+}
+
+# Mac
+if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) ] } {
+   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+		create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tx_clk_${x}$TO_THE_VARIATION_NAME" ]
+		create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}rx_clk_${x}$TO_THE_VARIATION_NAME" ]
+   }}
+
+# MacPcs
+if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
+   for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+		create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_tx_clk_${x}$TO_THE_VARIATION_NAME" ]
+		create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_rx_clk_${x}$TO_THE_VARIATION_NAME" ]
+   }}
+
+# MacPcsPma
+if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
+	#Constrain transceiver reference clock
+	create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports  "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
+}
+
+# MacPcs+SGMII
+if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
+	#Constrain transceiver reference clock
+	create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports  "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
+}
+
+# MacPcs+SGMII ( with or without PMA )
+if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_SGMII == 1)] } {
+
+}
+
+#  pmaAlt4Gxb
+if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
+  
+}
+
+#  macPcsPmaLvdsSgmii
+if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
+	#Cut the timing path betweeen unrelated clock domains
+}
+
+#  macPcsPmaLvdsNoSgmii
+if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
+}
+
+#  macPcsPmaTransceiverSgmii=
+if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
+	#Cut the timing path betweeen unrelated clock domains
+}
+
+#  macPcsPmaTransceiverNoSgmii=
+if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
+	#Cut the timing path betweeen unrelated clock domains
+}
+
+if { [ expr ($IS_SOPC == 0) ] } {
+	if { [ expr ($IS_FIFOLESS == 1) ] } {
+		create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_rx_afull_clk  [get_ports "${SYSTEM_PATH_PREFIX}rx_afull_clk$TO_THE_VARIATION_NAME" ]
+	}
+}
+
+derive_pll_clocks
+
+set clocks_list [get_clocks *]
+
+   foreach_in_collection clock $clocks_list {
+   	set name [get_clock_info -name $clock]
+    		if {[ expr [regexp "altera_tse" $name] == 1]} {
+        		set_clock_groups -exclusive -group [get_clocks $name]
+    		   }
+   	}
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+if { [ expr ($IS_SGMII == 1)] } {
+    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
+    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|b_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
+    set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|wr_g_rptr[*]}]
+    set_false_path -from [get_registers {*|altera_tse_top_sgmii*:U_SGMII|altera_tse_colision_detect:U_COL|state*}] -to [get_registers {*|altera_tse_fifoless_mac_tx:U_TX|gm_rx_col_reg*}]
+}
+
+}
+
+if { [ expr ($IS_HALFDUPLEX == 8) ] } {
+#Constrain timing for half duplex logic
+   if { [ expr ($IS_FIFOLESS == 0) ] } {
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|eop[1]]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|sop[1]]
+      set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers  *|altera_tse_mac_tx:U_TX|rd_1[*]]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+   }
+}
+
+if { [ expr ($IS_HALFDUPLEX == 32) ] } {
+#Constrain timing for half duplex logic
+   if { [ expr ($IS_FIFOLESS == 0) ] } {
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+      set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+   }
+}
+
+if { [ expr ($IS_HALFDUPLEX == 8) ] } {
+#Constrain timing for half duplex logic
+   if { [ expr ($IS_FIFOLESS == 1) ] } {
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
+      
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+      set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
+   }
+}
+
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds_constraints.tcl
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds_constraints.tcl
+#####################################################################################
+# Copyright (C) 1991-2009 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+#####################################################################################
+
+#####################################################################################
+# Altera Triple-Speed Ethernet Megacore TCL constraint file
+#
+# Generated on Wed Jun 16 16:45:07 CEST 2010
+#
+#####################################################################################
+# General Option
+set IS_SOPC 0
+set VARIATION_NAME "ip_stratixiv_tse_sgmii_lvds"
+set DEVICE_FAMILY "STRATIXIV"
+set FROM_THE_VARIATION_NAME ""
+set TO_THE_VARIATION_NAME ""
+
+# MAC Option
+set IS_MAC 1
+set NUMBER_OF_CHANNEL 1
+set IS_SMALLMAC 0
+set IS_SMALLMAC_GIGE 0
+set IS_FIFOLESS 0
+set IS_HALFDUPLEX 0
+set MII_INTERFACE "MII_GMII"
+
+# PCS Option
+set IS_PCS 1
+set IS_SGMII 0
+
+# PMA Option
+set IS_PMA 1
+set TRANSCEIVER_TYPE 1
+
+# GXB Option
+set IS_POWERDOWN 0
+
+
+if { [ expr ( $IS_SOPC == 1 )] } {
+
+    set FROM_THE_VARIATION_NAME "_from_the_$VARIATION_NAME"
+    set TO_THE_VARIATION_NAME "_to_the_$VARIATION_NAME"
+
+} else {
+
+    set FROM_THE_VARIATION_NAME ""
+    set TO_THE_VARIATION_NAME ""
+
+}
+
+
+if { [ expr ( $IS_FIFOLESS == 0 )] } {
+
+#  macPcs=
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0)] } {
+      #Optimize I/O timing for TBI interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d${TO_THE_VARIATION_NAME}
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d${FROM_THE_VARIATION_NAME}
+   } 
+
+# pcs=
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0)] } {
+      #Optimize I/O timing for MII interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_en
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_col
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_crs
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_en
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_err
+
+      #Optimize I/O timing for GMII interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_en
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_dv
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_err
+
+      #Optimize I/O timing for TBI interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d
+      }
+
+# pcsPma=
+   if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1)] } {
+      #Optimize I/O timing for MII interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_en
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_col
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_crs
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_en
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_err
+
+      #Optimize I/O timing for GMII interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_en
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_dv
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_err
+   }
+
+
+# pmaTransceiver=
+
+   if { [ expr ($IS_PCS == 1) && ($IS_PMA == 1)] } {
+      if { [ expr ($TRANSCEIVER_TYPE == 0)] } {
+         if { [string match $DEVICE_FAMILY "STRATIXIV"]} {
+            #Optimize I/O timing for serdes interface
+            set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to txp
+            set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rxp
+         } else {
+
+            # pmaTransceiverStratixIV=
+            #Optimize I/O timing for serdes interface
+            set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to txp
+            set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rxp
+         }
+      } 
+
+      if { [ expr ($TRANSCEIVER_TYPE == 1)] } {
+         # pmaLvds=
+   
+         #Constrain MAC PCS reference clock
+         set_instance_assignment -name GLOBAL_SIGNAL ON -to ref_clk
+
+         #Optimize I/O timing for serdes interface
+         set_instance_assignment -name IO_STANDARD LVDS -to ref_clk
+         set_instance_assignment -name IO_STANDARD LVDS -to txp
+         set_instance_assignment -name IO_STANDARD LVDS -to rxp
+      }
+   }
+
+
+# gmii=
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) && ([string match $MII_INTERFACE "MII_GMII"]) ] } {
+      #Optimize I/O timing for GMII network-side interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_dv
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_en
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_err
+	  
+	  #Optimize I/O timing for MII network-side interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_col
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_crs
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_d
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_en
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_err
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_d
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_en
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_err
+   }
+
+
+
+# rgmii=
+   if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) && ([string match $MII_INTERFACE "RGMII"])] } {
+      #Optimize I/O timing for RGMII network-side interface
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to rx_control
+      set_instance_assignment -name FAST_INPUT_REGISTER ON -to rgmii_in
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tx_control
+      set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rgmii_out
+   }
+
+} else {
+
+   if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) ] } {
+   
+		set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
+                set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
+
+      for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+
+
+		if { [ expr [string match $MII_INTERFACE "MII_GMII"] ] } {
+
+			#Optimize I/O timing for MII network-side interface
+			if { [ expr $IS_HALFDUPLEX == 1 ] } {
+				set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_col_${x}${TO_THE_VARIATION_NAME}
+				set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_crs_${x}${TO_THE_VARIATION_NAME}
+			}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_d_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_en_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_err_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_d_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_en_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_err_${x}${FROM_THE_VARIATION_NAME}
+
+			#Optimize I/O timing for GMII network-side interface
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_d_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_dv_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_err_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_d_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_en_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_err_${x}${FROM_THE_VARIATION_NAME}
+			
+			set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to rx_clk_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to tx_clk_${x}${TO_THE_VARIATION_NAME}
+			
+		} 
+
+		if { [ expr [string match $MII_INTERFACE "RGMII"] ] } {
+
+			#Optimize I/O timing for RGMII network-side interface
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to rx_control_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_INPUT_REGISTER ON -to rgmii_in_${x}${TO_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tx_control_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rgmii_out_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to rx_clk_${x}${TO_THE_VARIATION_NAME}
+			#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to tx_clk_${x}${TO_THE_VARIATION_NAME}
+			
+			
+		}
+
+	}
+}
+
+   if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
+		set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
+                set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
+		set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ref_clk${TO_THE_VARIATION_NAME}
+
+       for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+	   #Optimize I/O timing for TBI interface
+	   set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d_${x}${TO_THE_VARIATION_NAME}
+	   set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d_${x}${FROM_THE_VARIATION_NAME}
+	   set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to tbi_rx_clk_${x}${FROM_THE_VARIATION_NAME}
+	}
+   }
+
+
+   if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
+		set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
+                set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
+		set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ref_clk${TO_THE_VARIATION_NAME}
+   }
+
+
+   if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 0) ] } {
+      for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+	  if { [string match $DEVICE_FAMILY "STRATIXIV"]} {
+            #Optimize I/O timing for serdes interface
+            set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to txp_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rxp_${x}${TO_THE_VARIATION_NAME}
+         } else {
+            #Optimize I/O timing for serdes interface
+            set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to txp_${x}${FROM_THE_VARIATION_NAME}
+			set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rxp_${x}${TO_THE_VARIATION_NAME}
+         }
+	
+      }
+   }
+
+
+   if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 1) ] } {
+        
+        set_instance_assignment -name IO_STANDARD LVDS -to ref_clk${TO_THE_VARIATION_NAME}
+  
+        for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
+		set_instance_assignment -name IO_STANDARD LVDS -to txp_${x}${FROM_THE_VARIATION_NAME}
+		set_instance_assignment -name IO_STANDARD LVDS -to rxp_${x}${TO_THE_VARIATION_NAME}
+	}
+   }
+
+}
+
+export_assignments
+
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_ip_stratixiv_tse_sgmii_lvds IS
+END tb_ip_stratixiv_tse_sgmii_lvds;
+
+
+ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
+
+  CONSTANT sys_clk_period             : TIME := 10 ns;  -- 100 MHz
+  CONSTANT eth_clk_period             : TIME :=  8 ns;  -- 125 MHz
+  
+  CONSTANT c_tse_reg_addr_w           : NATURAL := 8;         -- = max 256 MAC registers
+  CONSTANT c_tse_byte_addr_w          : NATURAL := c_tse_reg_addr_w + 2;
+  CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#;   -- table 4.8, 4.9 in ug_ethernet.pdf
+  CONSTANT c_tse_data_w               : NATURAL := c_word_w;  -- = 32
+  
+  CONSTANT c_tse_symbol_w             : NATURAL := c_byte_w;                       -- = 8
+  CONSTANT c_tse_symbol_max           : NATURAL := 2**c_tse_symbol_w-1;            -- = 255
+  CONSTANT c_tse_symbols_per_beat     : NATURAL := c_tse_data_w / c_tse_symbol_w;  -- = 4
+  
+  CONSTANT c_tse_pcs_reg_addr_w       : NATURAL := 5;         -- = max 32 PCS registers
+  CONSTANT c_tse_pcs_halfword_addr_w  : NATURAL := c_tse_pcs_reg_addr_w + 1;  -- table 4.17 in ug_ethernet.pdf
+  CONSTANT c_tse_pcs_byte_addr_w      : NATURAL := c_tse_pcs_reg_addr_w + 2;
+  CONSTANT c_tse_pcs_data_w           : NATURAL := c_halfword_w;  -- = 16;
+  
+  CONSTANT c_tse_empty_w              : NATURAL := 2;
+  CONSTANT c_tse_tx_error_w           : NATURAL := 1;
+  CONSTANT c_tse_rx_error_w           : NATURAL := 6;
+  CONSTANT c_tse_error_w              : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+  CONSTANT c_tse_err_stat_w           : NATURAL := 18;
+  CONSTANT c_tse_frm_type_w           : NATURAL := 4;
+  
+  CONSTANT c_tse_tx_fifo_depth        : NATURAL := 256;  -- nof words for Tx FIFO
+  CONSTANT c_tse_rx_fifo_depth        : NATURAL := 256;  -- nof words for Rx FIFO
+  
+  CONSTANT c_tse_promis_en            : BOOLEAN := FALSE;
+  --CONSTANT c_tse_promis_en            : BOOLEAN := TRUE;
+  
+  CONSTANT c_tx_data_type             : NATURAL := 1;  -- 0 = symbols, 1 = counter
+  CONSTANT c_tx_ready_latency         : NATURAL := 0;
+  CONSTANT c_nof_tx_not_valid         : NATURAL := 0;  -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+  
+  CONSTANT c_eth_dst_mac              : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10FA01020300";
+  CONSTANT c_eth_src_mac              : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"123456789ABC";  -- = 12-34-56-78-9A-BC
+  CONSTANT c_eth_ethertype            : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"10FA";
+
+  TYPE t_mm_bus IS RECORD
+    -- Master In Slave Out
+    waitreq   : STD_LOGIC;
+    rddata    : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+    -- Master Out Slave In
+    address   : STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+    wrdata    : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+    wr        : STD_LOGIC;
+    rd        : STD_LOGIC;
+  END RECORD;
+
+  PROCEDURE proc_dbg_mm_bus(SIGNAL mm_miso  : IN  t_mm_bus;
+                            SIGNAL mm_mosi  : IN  t_mm_bus;
+                            SIGNAL dbg_mm   : OUT t_mm_bus) IS
+  BEGIN
+    dbg_mm.waitreq <= mm_miso.waitreq;
+    dbg_mm.rddata  <= mm_miso.rddata;
+    dbg_mm.address <= mm_mosi.address;
+    dbg_mm.wrdata  <= mm_mosi.wrdata;
+    dbg_mm.wr      <= mm_mosi.wr;
+    dbg_mm.rd      <= mm_mosi.rd;
+  END proc_dbg_mm_bus;
+  
+  -- Wait for MM access (either read or write) finished
+  PROCEDURE proc_mm_access(SIGNAL mm_clk      : IN  STD_LOGIC;
+                           SIGNAL mm_waitreq  : IN  STD_LOGIC;
+                           SIGNAL mm_access   : OUT STD_LOGIC) IS
+  BEGIN
+    mm_access <= '1';
+    WAIT UNTIL rising_edge(mm_clk);
+    WHILE mm_waitreq='1' LOOP
+      WAIT UNTIL rising_edge(mm_clk);
+    END LOOP;
+    mm_access <= '0';
+  END proc_mm_access;
+  
+  -- Use word addressing for MAC registers according to table 4.8, 4.9
+  PROCEDURE proc_wr_mac(CONSTANT mac_addr : IN  NATURAL;
+                        CONSTANT mac_data : IN  NATURAL;
+                        SIGNAL   mm_clk   : IN  STD_LOGIC;
+                        SIGNAL   mm_miso  : IN  t_mm_bus;
+                        SIGNAL   mm_mosi  : OUT t_mm_bus) IS
+  BEGIN
+    mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+    mm_mosi.wrdata  <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_data, c_tse_data_w));
+    proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+  END proc_wr_mac;
+  
+  PROCEDURE proc_rd_mac(CONSTANT mac_addr : IN  NATURAL;
+                        SIGNAL   mac_data : OUT NATURAL;
+                        SIGNAL   mm_clk   : IN  STD_LOGIC;
+                        SIGNAL   mm_miso  : IN  t_mm_bus;
+                        SIGNAL   mm_mosi  : OUT t_mm_bus) IS
+  BEGIN
+    mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+    proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+    MAC_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata));
+  END proc_rd_mac;
+  
+  -- Use halfword addressing for PCS register to match table 4.17
+  PROCEDURE proc_wr_pcs(CONSTANT pcs_addr : IN  NATURAL;
+                        CONSTANT pcs_data : IN  NATURAL;
+                        SIGNAL   mm_clk   : IN  STD_LOGIC;
+                        SIGNAL   mm_miso  : IN  t_mm_bus;
+                        SIGNAL   mm_mosi  : OUT t_mm_bus) IS
+  BEGIN
+    mm_mosi.address                             <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+    mm_mosi.wrdata                              <= (OTHERS=>'0');
+    mm_mosi.wrdata(c_tse_pcs_data_w-1 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_data, c_tse_pcs_data_w));
+    proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+  END proc_wr_pcs;
+
+  PROCEDURE proc_rd_pcs(CONSTANT pcs_addr : IN  NATURAL;
+                        SIGNAL   pcs_data : OUT NATURAL;
+                        SIGNAL   mm_clk   : IN  STD_LOGIC;
+                        SIGNAL   mm_miso  : IN  t_mm_bus;
+                        SIGNAL   mm_mosi  : OUT t_mm_bus) IS
+  BEGIN
+    mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+    proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+    pcs_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata(c_tse_pcs_data_w-1 DOWNTO 0)));
+  END proc_rd_pcs;
+  
+  TYPE t_tse_stream IS RECORD
+    -- Source In or Sink Out
+    ready    : STD_LOGIC;
+    -- Source Out or Sink In
+    data     : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+    valid    : STD_LOGIC;
+    sop      : STD_LOGIC;
+    eop      : STD_LOGIC;
+    empty    : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+    err      : STD_LOGIC_VECTOR(c_tse_error_w-1 DOWNTO 0);
+  END RECORD;
+    
+  PROCEDURE proc_dbg_tse_stream_src(SIGNAL src_in  : IN  t_tse_stream;
+                                    SIGNAL src_out : IN  t_tse_stream;
+                                    SIGNAL dbg_src : OUT t_tse_stream) IS
+  BEGIN
+    dbg_src.ready <= src_in.ready;
+    dbg_src.data  <= src_out.data;
+    dbg_src.valid <= src_out.valid;
+    dbg_src.sop   <= src_out.sop;
+    dbg_src.eop   <= src_out.eop;
+    dbg_src.empty <= src_out.empty;
+    dbg_src.err   <= src_out.err;
+  END proc_dbg_tse_stream_src;
+  
+  PROCEDURE proc_dbg_tse_stream_snk(SIGNAL snk_in  : IN  t_tse_stream;
+                                    SIGNAL snk_out : IN  t_tse_stream;
+                                    SIGNAL dbg_snk : OUT t_tse_stream) IS
+  BEGIN
+    dbg_snk.ready <= snk_out.ready;
+    dbg_snk.data  <= snk_in.data;
+    dbg_snk.valid <= snk_in.valid;
+    dbg_snk.sop   <= snk_in.sop;
+    dbg_snk.eop   <= snk_in.eop;
+    dbg_snk.empty <= snk_in.empty;
+    dbg_snk.err   <= snk_in.err;
+  END proc_dbg_tse_stream_snk;
+  
+  -- Handle TX ready
+  -- Only support tx_ready_latency=0 or 1, corresponding to TX_ALMOST_FULL=3 or 4
+  -- Support for tx_ready_latency>1 requires keeping previous ready information
+  -- in a STD_LOGIC_VECTOR(tx_ready_latency-1 DOWNTO 0).
+  PROCEDURE proc_ready_latency(CONSTANT c_latency : IN  NATURAL;
+                               SIGNAL   clk       : IN  STD_LOGIC;
+                               SIGNAL   ready     : IN  STD_LOGIC;
+                               CONSTANT c_valid   : IN  STD_LOGIC;
+                               CONSTANT c_sop     : IN  STD_LOGIC;
+                               CONSTANT c_eop     : IN  STD_LOGIC;
+                               SIGNAL   out_valid : OUT STD_LOGIC;
+                               SIGNAL   out_sop   : OUT STD_LOGIC;
+                               SIGNAL   out_eop   : OUT STD_LOGIC) IS
+  BEGIN
+    IF c_latency=0 THEN
+      out_valid <= c_valid;
+      out_sop   <= c_sop;
+      out_eop   <= c_eop;
+      WAIT UNTIL rising_edge(clk);
+      WHILE ready /= '1' LOOP
+        WAIT UNTIL rising_edge(clk);
+      END LOOP;
+    END IF;
+    IF c_latency=1 THEN
+      WHILE ready /= '1' LOOP
+        out_valid <= '0';
+        out_sop   <= '0';
+        out_eop   <= '0';
+        WAIT UNTIL rising_edge(clk);
+      END LOOP;
+      out_valid <= c_valid;
+      out_sop   <= c_sop;
+      out_eop   <= c_eop;
+      WAIT UNTIL rising_edge(clk);
+    END IF;
+  END proc_ready_latency;
+  
+  -- Transmit user packet
+  -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+  -- . Packets can be send immediately after eachother so new sop directly after last eop
+  -- . The word rate is controlled by respecting ready from the MAC
+  PROCEDURE proc_tx_packet(CONSTANT dst_mac_addr : IN  STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+                           CONSTANT src_mac_addr : IN  STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+                           CONSTANT ethertype    : IN  STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+                           CONSTANT data_len     : IN  NATURAL;  -- in symbols = octets = bytes
+                           SIGNAL   dp_clk       : IN  STD_LOGIC;
+                           SIGNAL   dp_src_in    : IN  t_tse_stream;
+                           SIGNAL   dp_src_out   : OUT t_tse_stream) IS
+    CONSTANT c_mod            : NATURAL := data_len MOD c_tse_symbols_per_beat;
+    CONSTANT c_nof_data_beats : NATURAL := data_len   / c_tse_symbols_per_beat + sel_a_b(c_mod, 1, 0);
+    CONSTANT c_empty          : NATURAL := sel_a_b(c_mod, c_tse_symbols_per_beat - c_mod, 0);
+    VARIABLE v_sym            : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+    VARIABLE v_num            : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+  BEGIN
+    -- DST MAC
+    dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+    dp_src_out.data              <= (OTHERS=>'0');
+    dp_src_out.data(15 DOWNTO 0) <= htons(dst_mac_addr(15 DOWNTO 0));  -- send to itself
+    proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+    dp_src_out.data  <= htonl(dst_mac_addr(47 DOWNTO 16));
+    proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+    -- SRC MAC
+    dp_src_out.data  <= htonl(src_mac_addr(31 DOWNTO 0));
+    proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+    -- SRC MAC & ETHERTYPE
+    dp_src_out.data  <= htons(src_mac_addr(47 DOWNTO 32)) & htons(c_eth_ethertype);
+    -- DATA
+    FOR I IN 0 TO c_nof_data_beats-1 LOOP
+      proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+      IF c_tx_data_type=0 THEN
+        -- data : X"01020304", X"05060708", X"090A0B0C", etc
+        FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+          v_sym := v_sym + 1;
+          dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= STD_LOGIC_VECTOR(v_sym);
+        END LOOP;
+      ELSE
+        -- data : X"00000001", X"00000002", X"00000003", etc
+        v_num := v_num + 1;
+        dp_src_out.data <= STD_LOGIC_VECTOR(v_num);
+      END IF;
+      -- tb : pull valid low for some time during the middle of the payload
+      IF c_nof_tx_not_valid > 0 AND I=c_nof_data_beats/2 THEN
+        dp_src_out.valid <= '0';
+        FOR I IN 0 TO c_nof_tx_not_valid LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+        dp_src_out.valid <= '1';
+      END IF;
+    END LOOP;
+    IF c_empty > 0 THEN
+      dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(c_empty, c_tse_empty_w));
+      FOR J IN c_empty-1 DOWNTO 0 LOOP
+        dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= (OTHERS=>'0');
+      END LOOP;
+    END IF;
+    proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '1', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+    dp_src_out.data  <= (OTHERS=>'0');
+    dp_src_out.valid <= '0';
+    dp_src_out.eop   <= '0';
+    dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+  END proc_tx_packet;
+
+  PROCEDURE proc_valid_sop(SIGNAL   clk       : IN  STD_LOGIC;
+                           SIGNAL   in_valid  : IN  STD_LOGIC;
+                           SIGNAL   in_sop    : IN  STD_LOGIC) IS
+  BEGIN
+    WAIT UNTIL rising_edge(clk);
+    WHILE in_valid /= '1' AND in_sop /= '1' LOOP
+      WAIT UNTIL rising_edge(clk);
+    END LOOP;
+  END proc_valid_sop;
+  
+  PROCEDURE proc_valid(SIGNAL   clk       : IN  STD_LOGIC;
+                       SIGNAL   in_valid  : IN  STD_LOGIC) IS
+  BEGIN
+    WAIT UNTIL rising_edge(clk);
+    WHILE in_valid /= '1' LOOP
+      WAIT UNTIL rising_edge(clk);
+    END LOOP;
+  END proc_valid;
+  
+  -- Receive packet
+  -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+  -- . Packets can be always be received, assume the user application is always ready
+  -- . The CRC32 is also passed on to the user at eop.
+  -- . Note that when empty/=0 then the CRC32 is not word aligned, so therefore use prev_data to be able
+  --   to handle part of last data word in case empty/=0 at eop
+  PROCEDURE proc_rx_packet(CONSTANT dst_mac_addr : IN  STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+                           CONSTANT src_mac_addr : IN  STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+                           CONSTANT ethertype    : IN  STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+                           SIGNAL   dp_clk       : IN  STD_LOGIC;
+                           SIGNAL   dp_snk_in    : IN  t_tse_stream;
+                           SIGNAL   dp_snk_out   : OUT t_tse_stream) IS
+    VARIABLE v_sym            : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+    VARIABLE v_num            : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+    VARIABLE v_empty          : NATURAL;
+    VARIABLE v_first          : BOOLEAN := TRUE;
+    VARIABLE v_data           : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+    VARIABLE v_prev_data      : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+  BEGIN
+    -- Keep ff_rx_snk_out.ready='1' all the time
+    dp_snk_out.ready <= '1';
+    -- Verify DST MAC
+    proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
+    ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000"                            REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+    ASSERT dp_snk_in.data(15 DOWNTO  0) = htons(dst_mac_addr(15 DOWNTO 0))   REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+    proc_valid(dp_clk, dp_snk_in.valid);
+    ASSERT dp_snk_in.data(31 DOWNTO  0) = htonl(dst_mac_addr(47 DOWNTO 16))  REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+    -- Verify SRC MAC
+    proc_valid(dp_clk, dp_snk_in.valid);
+    ASSERT dp_snk_in.data(31 DOWNTO  0) = htonl(src_mac_addr(31 DOWNTO 0))   REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+    -- Verify SRC MAC & ETHERTYPE
+    proc_valid(dp_clk, dp_snk_in.valid);
+    ASSERT dp_snk_in.data(31 DOWNTO 16) = htons(src_mac_addr(47 DOWNTO 32))  REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+    ASSERT dp_snk_in.data(15 DOWNTO  0) = htons(c_eth_ethertype)             REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+    -- Verify DATA
+    v_first := TRUE;
+    proc_valid(dp_clk, dp_snk_in.valid);
+    WHILE dp_snk_in.eop /= '1' LOOP
+      v_prev_data := v_data;
+      v_data      := dp_snk_in.data;
+      IF v_first = FALSE THEN
+        IF c_tx_data_type=0 THEN
+          -- data : X"01020304", X"05060708", X"090A0B0C", etc
+          FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+            v_sym := v_sym + 1;
+            ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong data symbol" SEVERITY ERROR;
+          END LOOP;
+        ELSE
+          -- data : X"00000001", X"00000002", X"00000003", etc
+          v_num := v_num + 1;
+          ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong data word" SEVERITY ERROR;
+        END IF;
+      END IF;
+      v_first := FALSE;
+      proc_valid(dp_clk, dp_snk_in.valid);
+    END LOOP;
+    -- Verify last DATA and CRC32 if empty /=0 else the last word is only the CRC32
+    v_prev_data := v_data;
+    v_data      := dp_snk_in.data;
+    v_empty     := TO_INTEGER(UNSIGNED(dp_snk_in.empty));
+    IF v_empty > 0 THEN
+      FOR J IN v_empty-1 DOWNTO 0 LOOP
+        v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');
+      END LOOP;
+      IF c_tx_data_type=0 THEN
+        -- data : X"01020304", X"05060708", X"090A0B0C", etc
+        FOR J IN c_tse_symbols_per_beat-1 DOWNTO v_empty LOOP  -- ignore CRC32 symbols in last data word
+          v_sym := v_sym + 1;
+          ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong empty data symbol" SEVERITY ERROR;
+        END LOOP;
+      ELSE
+        -- data : X"00000001", X"00000002", X"00000003", etc
+        v_num := v_num + 1;
+        FOR J IN v_empty-1 DOWNTO 0 LOOP
+          v_num((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');  -- force CRC32 symbols in last data word to 0
+        END LOOP;
+        ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong empty data word" SEVERITY ERROR;
+      END IF;
+    ELSE
+      -- No verify on CRC32 word
+    END IF;
+  END proc_rx_packet;
+
+  
+  -- Clocks and reset
+  SIGNAL eth_clk        : STD_LOGIC := '0';
+  SIGNAL sys_clk        : STD_LOGIC := '0';
+  SIGNAL dp_clk         : STD_LOGIC;
+  SIGNAL mm_clk         : STD_LOGIC;
+  SIGNAL mm_rst         : STD_LOGIC;
+  
+  -- TSE MAC control interface
+  SIGNAL mm_init        : STD_LOGIC := '1';                 
+  SIGNAL mm_miso        : t_mm_bus;  -- master in  slave out
+  SIGNAL mm_mosi        : t_mm_bus;  -- master out slave in
+  
+  SIGNAL pcs_rddata     : NATURAL;  -- [c_tse_pcs_data_w-1:0]
+             
+  SIGNAL tse_led_an     : STD_LOGIC;
+  SIGNAL tse_led_link   : STD_LOGIC;
+    
+  -- TSE MAC transmit interface
+  -- . Avalon ST source
+  SIGNAL ff_tx_src_in   : t_tse_stream;
+  SIGNAL ff_tx_src_out  : t_tse_stream;
+  -- . MAC specific
+  SIGNAL ff_tx_crc_fwd  : STD_LOGIC;
+  SIGNAL ff_tx_septy    : STD_LOGIC;
+  SIGNAL ff_tx_a_full   : STD_LOGIC;
+  SIGNAL ff_tx_a_empty  : STD_LOGIC;
+  SIGNAL ff_tx_uflow    : STD_LOGIC;
+  
+  -- TSE MAC receive interface
+  -- . Avalon ST sink
+  SIGNAL ff_rx_snk_in   : t_tse_stream;
+  SIGNAL ff_rx_snk_out  : t_tse_stream;
+  -- . MAC specific
+  SIGNAL ff_rx_ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+  SIGNAL ff_rx_frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+  SIGNAL ff_rx_dsav     : STD_LOGIC;
+  SIGNAL ff_rx_a_full   : STD_LOGIC;
+  SIGNAL ff_rx_a_empty  : STD_LOGIC;
+  
+  -- TSE PHY interface
+  SIGNAL eth_txp        : STD_LOGIC;
+  SIGNAL eth_rxp        : STD_LOGIC;
+  
+  -- Debug signals to combine valid in and out of records
+  SIGNAL dbg_mm         : t_mm_bus;
+  SIGNAL dbg_ff_tx      : t_tse_stream;
+  SIGNAL dbg_ff_rx      : t_tse_stream;
+  
+BEGIN
+
+  eth_clk <= NOT eth_clk AFTER eth_clk_period/2;  -- TSE reference clock
+  sys_clk <= NOT sys_clk AFTER sys_clk_period/2;  -- System clock
+
+  mm_clk  <= sys_clk;
+  dp_clk  <= sys_clk;
+  
+  -- Debug signals to combine valid in and out of records
+  proc_dbg_mm_bus(        mm_miso,      mm_mosi,       dbg_mm);
+  proc_dbg_tse_stream_src(ff_tx_src_in, ff_tx_src_out, dbg_ff_tx);
+  proc_dbg_tse_stream_snk(ff_rx_snk_in, ff_rx_snk_out, dbg_ff_rx);
+  
+  -- run 1 us
+  p_mm_stimuli : PROCESS
+  BEGIN
+    mm_init  <= '1';
+    mm_mosi.wr <= '0';
+    mm_mosi.rd <= '0';
+    
+    -- reset release
+    mm_rst <= '1';
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+    mm_rst <= '0';
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+    
+    -- PSC control
+    proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- REV --> 0x0901
+    proc_wr_pcs(16#28#,   16#0008#, mm_clk, mm_miso, mm_mosi);  -- IF_MODE <-- Force 1GbE, no autonegatiation
+    proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- CONTROL --> 0x1140
+    proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- STATUS --> 0x000D
+    proc_wr_pcs(16#00#,   16#0140#, mm_clk, mm_miso, mm_mosi);  -- CONTROL <-- Auto negotiate disable
+    
+    -- MAC control
+    proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- REV --> CUST_VERSION & 0x0901
+    IF c_tse_promis_en=FALSE THEN
+      proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+    ELSE
+      proc_wr_mac(16#008#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+    END IF;
+      -- COMMAND_CONFIG <--
+      -- Only the bits relevant to UniBoard are explained here, others are 0
+      -- [    0] = TX_ENA             = 1, enable tx datapath
+      -- [    1] = RX_ENA             = 1, enable rx datapath
+      -- [    2] = XON_GEN            = 0
+      -- [    3] = ETH_SPEED          = 1, enable 1GbE operation
+      -- [    4] = PROMIS_EN          = 0, when 1 then receive all frames
+      -- [    5] = PAD_EN             = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+      -- [    6] = CRC_FWD            = 1, enable receive CRC forward
+      -- [    7] = PAUSE_FWD          = 0
+      -- [    8] = PAUSE_IGNORE       = 0
+      -- [    9] = TX_ADDR_INS        = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+      -- [   10] = HD_ENA             = 0
+      -- [   11] = EXCESS_COL         = 0
+      -- [   12] = LATE_COL           = 0
+      -- [   13] = SW_RESET           = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+      -- [   14] = MHAS_SEL           = 0, select multicast address resolutions hash-code mode
+      -- [   15] = LOOP_ENA           = 0
+      -- [18-16] = TX_ADDR_SEL[2:0]   = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+      -- [   19] = MAGIC_EN           = 0
+      -- [   20] = SLEEP              = 0
+      -- [   21] = WAKEUP             = 0
+      -- [   22] = XOFF_GEN           = 0
+      -- [   23] = CNT_FRM_ENA        = 0
+      -- [   24] = NO_LGTH_CHECK      = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+      -- [   25] = ENA_10             = 0
+      -- [   26] = RX_ERR_DISC        = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+      --                                   when 0 then pass on with rx_err[0]=1
+      -- [   27] = DISABLE_RD_TIMEOUT = 0
+      -- [30-28] = RSVD               = 000
+      -- [   31] = CNT_RESET          = 0, when 1 clear statistics
+    proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi);  -- MAC_0
+    proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi);  -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+    proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);  -- TX_IPG_LENGTH <-- interpacket gap = 12
+    proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi);  -- FRM_LENGTH <-- receive max frame length = 1518
+    
+    -- FIFO legenda:
+    -- . Tx section full  = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+    -- . Rx section full  = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+    -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+    -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+    -- . Tx almost full   = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+    --                      so choose 3 for zero tx ready latency
+    -- . Rx almost full   = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+    --                      --> break off the reception with an error to avoid FIFO overflow
+    -- . Tx almost empty  = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+    --                      --> break off the transmission with an error to avoid FIFO underflow
+    -- . Rx almost empty  = Assert ff_rx_a_empty
+    -- Typical FIFO values:
+    -- . TX_SECTION_FULL  = 16   > 8   = TX_ALMOST_EMPTY
+    -- . RX_SECTION_FULL  = 16   > 8   = RX_ALMOST_EMPTY
+    -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+    -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+    -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+    --                         ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+    -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+    proc_wr_mac(16#01C#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi);  -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+    proc_wr_mac(16#020#,                     16, mm_clk, mm_miso, mm_mosi);  -- RX_SECTION_FULL  <-- default 16
+    proc_wr_mac(16#024#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi);  -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+    proc_wr_mac(16#028#,                     16, mm_clk, mm_miso, mm_mosi);  -- TX_SECTION_FULL  <-- default 16, >~ 8 otherwise no tx
+    proc_wr_mac(16#02C#,                      8, mm_clk, mm_miso, mm_mosi);  -- RX_ALMOST_EMPTY  <-- default 8
+    proc_wr_mac(16#030#,                      8, mm_clk, mm_miso, mm_mosi);  -- RX_ALMOST_FULL   <-- default 8
+    proc_wr_mac(16#034#,                      8, mm_clk, mm_miso, mm_mosi);  -- TX_ALMOST_EMPTY  <-- default 8
+    proc_wr_mac(16#038#,   c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi);  -- TX_ALMOST_FULL   <-- default 3
+    
+    proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+    proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi);  -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+    
+    WAIT UNTIL rising_edge(mm_clk);
+    mm_init <= '0';
+    
+    WAIT;
+  END PROCESS;
+
+  p_tx_frame : PROCESS
+  BEGIN
+    -- . Avalon ST
+    ff_tx_src_out.data  <= (OTHERS=>'0');
+    ff_tx_src_out.valid <= '0';
+    ff_tx_src_out.sop   <= '0';
+    ff_tx_src_out.eop   <= '0';
+    ff_tx_src_out.empty <= (OTHERS=>'0');
+    ff_tx_src_out.err   <= (OTHERS=>'0');
+    -- . MAC specific
+    ff_tx_crc_fwd <= '0';
+    
+    WHILE mm_init/='0' LOOP
+      WAIT UNTIL rising_edge(dp_clk);
+    END LOOP;
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+    
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000",   16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype,   16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+    proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out);  -- verify st empty
+    proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+--     proc_tx_packet(c_eth_src_mac, c_eth_src_mac,    c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+    
+    
+    WAIT;
+  END PROCESS;
+  
+  p_rx_frame : PROCESS
+  BEGIN
+    -- . Avalon ST
+    ff_rx_snk_out.ready <= '0';
+    
+    WHILE mm_init/='0' LOOP
+      WAIT UNTIL rising_edge(dp_clk);
+    END LOOP;
+    
+    -- Receive forever
+    WHILE TRUE LOOP
+      proc_rx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, dp_clk, ff_rx_snk_in, ff_rx_snk_out);
+    END LOOP;
+    
+    WAIT;
+  END PROCESS;
+  
+  dut : ENTITY work.ip_stratixiv_tse_sgmii_lvds
+    -- The ip_stratixiv_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+    -- . ENABLE_SHIFT16  = 1   : Align packet headers to 32 bit, useful for Nios data handling
+    -- . ENABLE_SUP_ADDR = 0   : An extra MAC addresses can e.g. be used as service MAC for tests
+    -- . ENA_HASH        = 0   : A multi cast hash table can be used to address all nodes at once
+    -- . STAT_CNT_ENA    = 0   : PHY statistics counts are useful for monitoring, but not realy needed
+    -- . EG_FIFO         = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+    -- . ING_FIFO        = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+  PORT MAP (
+    -- MAC transmit interface
+    -- . Avalon ST
+    ff_tx_clk     => dp_clk,
+    ff_tx_rdy     => ff_tx_src_in.ready,
+    ff_tx_data    => ff_tx_src_out.data,
+    ff_tx_wren    => ff_tx_src_out.valid,
+    ff_tx_sop     => ff_tx_src_out.sop,
+    ff_tx_eop     => ff_tx_src_out.eop,
+    ff_tx_mod     => ff_tx_src_out.empty,
+    ff_tx_err     => ff_tx_src_out.err(0),
+    -- . MAC specific
+    ff_tx_crc_fwd => ff_tx_crc_fwd,    -- when '0' MAC inserts CRC32 after eop
+    ff_tx_septy   => ff_tx_septy,      -- when '0' then tx FIFO goes above section-empty threshold
+    ff_tx_a_full  => ff_tx_a_full,     -- when '1' then tx FIFO goes above almost-full threshold
+    ff_tx_a_empty => ff_tx_a_empty,    -- when '1' then tx FIFO goes below almost-empty threshold
+    tx_ff_uflow   => ff_tx_uflow,      -- when '1' then tx FIFO underflow
+    -- MAC receive interface
+    -- . Avalon ST
+    ff_rx_clk     => dp_clk,
+    ff_rx_rdy     => ff_rx_snk_out.ready,
+    ff_rx_data    => ff_rx_snk_in.data,
+    ff_rx_dval    => ff_rx_snk_in.valid,
+    ff_rx_sop     => ff_rx_snk_in.sop,
+    ff_rx_eop     => ff_rx_snk_in.eop,
+    ff_rx_mod     => ff_rx_snk_in.empty,
+    rx_err        => ff_rx_snk_in.err, -- [5] collision error (can only occur in half duplex mode)
+                                       -- [4] PHY error on GMII
+                                       -- [3] receive frame truncated due to FIFO overflow
+                                       -- [2] CRC-32 error
+                                       -- [1] invalid length
+                                       -- [0] = OR of [1:5]
+    -- . MAC specific
+    rx_err_stat   => ff_rx_ethertype,  -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+    rx_frm_type   => ff_rx_frm_type,   -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+    ff_rx_dsav    => ff_rx_dsav,       -- rx frame available, but not necessarily a complete frame
+    ff_rx_a_full  => ff_rx_a_full,     -- when '1' then rx FIFO goes above almost-full threshold 
+    ff_rx_a_empty => ff_rx_a_empty,    -- when '1' then rx FIFO goes below almost-empty threshold
+    -- Reset
+    reset         => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
+    -- MM control interface
+    clk           => mm_clk,
+    address       => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2),
+    readdata      => mm_miso.rddata,
+    read          => mm_mosi.rd,
+    writedata     => mm_mosi.wrdata,
+    write         => mm_mosi.wr,
+    waitrequest   => mm_miso.waitreq,
+    -- Status LEDs
+    led_an        => tse_led_an,      -- '1' = autonegation completed
+    led_link      => tse_led_link,    -- '1' = successful link synchronisation
+    led_disp_err  => OPEN,            -- TBI character error
+    led_char_err  => OPEN,            -- TBI disparity error
+    -- Serial 1.25 Gbps
+    ref_clk       => eth_clk,
+    txp           => eth_txp,
+    rxp           => eth_rxp    
+  );
+  
+  -- Loopback
+  eth_rxp <= eth_txp;
+      
+END tb;