Added new ddr versions

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg

+hdl_lib_name = unb1_test_ddr_MB_I_II
+hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib
+hdl_lib_uses_synth = unb1_board unb1_test
+hdl_lib_uses_sim = 
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
+
+hdl_lib_technology = ip_stratixiv
+
+synth_files =
+    unb1_test_ddr_MB_I_II.vhd
+    
+test_bench_files = 
+    tb_unb1_test_ddr_MB_I_II.vhd
+
+modelsim_copy_files =
+    ../../src/hex hex
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus/qsys_unb1_test.qsys .
+    ../../src/hex hex
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    
+quartus_tcl_files =
+    quartus/unb1_test_ddr_pins.tcl
+    ../../quartus/unb1_test_pins_constraints.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb1_test_ddr_MB_I_II.
+-- Description: see tb_unb1_test
+
+
+LIBRARY IEEE, unb1_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb1_test_ddr_MB_I_II IS
+END tb_unb1_test_ddr_MB_I_II;
+
+
+ARCHITECTURE tb OF tb_unb1_test_ddr_MB_I_II IS
+BEGIN
+  u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
+  GENERIC MAP (
+    g_design_name => "unb1_test_ddr_MB_I_II",
+    --g_sim_node_nr => 7 -- BN3
+    g_sim_node_nr => 0 --FN0
+  );
+END tb;

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+ENTITY unb1_test_ddr_MB_I_II IS
+  GENERIC (
+    g_design_name : STRING  := "unb1_test_ddr_MB_I_II"; -- use revision name = entity name = design name
+    g_design_note : STRING  := "Test Design with 2-ch ddr";
+    g_sim         : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0;  -- FN0
+    g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+    -- I2C Interface to Sensors
+    SENS_SC      : INOUT STD_LOGIC;
+    SENS_SD      : INOUT STD_LOGIC;
+
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC;
+    ETH_SGOUT    : OUT   STD_LOGIC;
+
+    -- SO-DIMM Memory Bank I
+    MB_I_IN      : IN    t_tech_ddr3_phy_in;
+    MB_I_IO      : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU      : OUT   t_tech_ddr3_phy_ou;
+
+    -- SO-DIMM Memory Bank II
+    MB_II_IN     : IN    t_tech_ddr3_phy_in;
+    MB_II_IO     : INOUT t_tech_ddr3_phy_io;
+    MB_II_OU     : OUT   t_tech_ddr3_phy_ou
+  );
+END unb1_test_ddr_MB_I_II;
+
+
+ARCHITECTURE str OF unb1_test_ddr_MB_I_II IS
+
+BEGIN
+
+  u_revision : ENTITY unb1_test_lib.unb1_test
+  GENERIC MAP (
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time,
+    g_stamp_svn   => g_stamp_svn
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => CLK,
+    PPS          => PPS,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => VERSION,
+    ID           => ID,
+    TESTIO       => TESTIO,
+
+    -- I2C Interface to Sensors
+    sens_sc      => sens_sc,
+    sens_sd      => sens_sd,
+
+    -- 1GbE Control Interface
+    ETH_clk      => ETH_clk,
+    ETH_SGIN     => ETH_SGIN,
+    ETH_SGOUT    => ETH_SGOUT,
+
+    -- SO-DIMM Memory Bank I
+    MB_I_IN      => MB_I_IN,
+    MB_I_IO      => MB_I_IO,
+    MB_I_OU      => MB_I_OU,
+
+    -- SO-DIMM Memory Bank II
+    MB_II_IN     => MB_II_IN,
+    MB_II_IO     => MB_II_IO,
+    MB_II_OU     => MB_II_OU
+  );
+
+END str;
+