Skip to content
Snippets Groups Projects
Commit 7f7f6d23 authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

Fixed qsys errors.

parent 888d2834
Branches
No related tags found
Loading
...@@ -18,12 +18,12 @@ ...@@ -18,12 +18,12 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author : J Hargreaves -- Author : R. van der Walle
-- Purpose: -- Purpose:
-- Wrapper for full adc input test design -- Wrapper for full filterbank test design
-- Description: -- Description:
-- Unb2b version for lab testing -- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams -- Contains complete AIT input stage with 12 ADC streams and FSUB
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib; LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
...@@ -39,7 +39,7 @@ USE dp_lib.dp_stream_pkg.ALL; ...@@ -39,7 +39,7 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_filterbank_full IS ENTITY lofar2_unb2b_filterbank_full IS
GENERIC ( GENERIC (
g_design_name : STRING := "lofar2_unb2b_filterbank_full"; g_design_name : STRING := "lofar2_unb2b_filterbank_full";
g_design_note : STRING := "Lofar2 adc with all streams"; g_design_note : STRING := "Lofar2 filterbank with all streams";
g_sim : BOOLEAN := FALSE; --Overridden by TB g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0;
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment